>> "they" who allegedly attempted to "try to sell us" hyped numbers, is it?

> Probably it's all managed from Bielefeld...

And now even the amigabounty.net team seems to be involved in the conspiracy suspected by takemehomegrandma:

"whoever "they" are, anybody knows?"
http://www.amiga.org/forums/showpost.php?p=701665

;-)

Update:

> Description of the relevant FTF 2012 session (FTF-IND-F0016) now online:
> "This session describes new instructions for extended support for misaligned
> vectors, support for handling head and tail vectors, and the long-awaited capability
> to move from general purpose to vector registers. Learn about the performance
> improvements resulting from enhancement to both AltiVec and the e6500 core."
> http://www.getregisterednow.com/FSL/CEX/Session.aspx?li=1

From the relevant FTF 2012 session slides:

"AltiVec e6500 core technology is essentially the same as AltiVec technology from the 74xx processors except the following:
· Adds new instructions for computing absolute differences [...]
· Adds new instructions for moving data from GPRs to VRs [...]
· Adds new instructions for dealing with misaligned vectors more easily [...]
· Adds new instructions for dealing with elements of vectors [...] These allow loading/storing of arbitrary elements to arbitrary addresses
[...]
Little-endian byte ordering is not supported on Power ISA AltiVec definition.
Data stream instructions [...] are not supported on Power ISA AltiVec definition.
[...]
IVORs added for AltiVec unavailable interrupt and AltiVec assist interrupt.
Move from GPR to VR [...] instructions move data from 2 GPRs into a vector register.
Absolute difference instructions [...] compute the unsigned absolute differences. These
are useful for motion estimation in video processing.
Extended support for misaligned vectors [...]
Extended support for handling head and tail of vectors [...]
External PID instructions for loading and storing VRs [...] for moving data efficiently across address spaces.
[...]
Data Stream Instructions [...] were present in the first definition of AltiVec technology for PowerPC processors. These instructions provided software initiated streaming prefetch controls. In Power ISA these instructions are no longer defined, and streaming is performed by variants of the dcbt instruction or by hardware prefetchers. Cache stashing could be considered an alternative as well. For Freescale EIS, these instructions are treated as no-ops since they may be present in older code and do not change architectural state.
[...]
Original AltiVec technology on the e600 core included an AltiVec unavailable exception. IVORs are the equivalent exception mechanism in e500-based cores. The AltiVec unavailable interrupt occurs when an attempt is made to execute an AltiVec instruction and MSR[SPV] = 0. This can be useful in reducing context switch overhead by not saving AltiVec registers unless a process actually uses AltiVec instructions. [...] In general, AltiVec vector instructions generate very few exceptions
[...]
Moving GPRs into a Vector Register [...] was a source of frustration in original AltiVec technology. The explanation was that the interconnect between GPRs and VPRs was not warranted when data could be moved quickly via store and load from L1 cache. Still, the capability was desired by many customers. These new instructions will make it simpler to program with AltiVec.
[...]
Absolute Difference Intructions [...] are useful for motion estimation in video processing.

AltiVec e6500 limitations
· Operates in big-endian only
· Does not have data streaming (dst type instructions) They are executed as NOPs
[...]
New Load and Store Instructions
· Reduces the effort to load and store unaligned (not quad-word aligned) data
· Reduces number of registers needed for permute and mask vectors
· Reduces the effort to deal with the head and tail of unaligned strings or vector arrays
· Improves performance through:
- Fewer instructions
- Less register pressure
- Less context to save
· Makes programming AltiVec technology simpler
[...]
Summary
· AltiVec technology is being "advanced" into the e6500 core (after skipping the e500 -- which had SPE, the e500mc, and the e5500) from the e600 core.
· New instructions to move data from GPRs to VRs will reduce complexity and instruction count.
· New load and store instructions simplify misaligned accesses and reduce complexity and instruction count."
http://www.freescale.com/files/training_pdf/FTF/2012/americas/WBNR_FTF12_IND_F0016.pdf (pages 4-14 and 32)
http://www.freescale.com/files/training/doc/dwf/DWF13_AMF_NET_T0015.pdf (pages 32-50)
http://www.freescale.com/files/training/doc/ftf/2014/FTF-NET-F0139.pdf (pages 15/16-25/26)

"AltiVec technology for the e6500 core is essentially the same as AltiVec technology from the e600 core, except for the following:
- Adds new instructions for computing absolute differences [...] These speed up in the inner loop of motion estimation video processing
- Adds new instructions for dealing with misaligned vectors more easily [...]
- Adds new instructions for dealing with elements of vectors [...] These allow loading/storing of arbitrary elements to arbitrary addresses
- Instructions for moving data from GPRn to vector register [...]

AltiVec technology for e6500 limitations
- Operates in big-endian only
- Does not have data streaming (dst type instructions) They are executed as NOPs"
http://www.freescale.com/files/training_pdf/FTF/2012/americas/WBNR_FTF12_NET_F0117.pdf (pages 45/46 and 48)
http://2012ftf.ccidnet.com/pdf/0381.pdf (pages 45/46 and 48)
http://www.freescale.com.cn/cstory/ftf/2012/pdf/0381.pdf (pages 45/46 and 48)


Edit: added more PDF links

[ Edited by Andreas_Wolf 21.04.2014 - 18:59 ]

@Andreas_Wolf,

Since you are more up-to-date on this topic, would you mind sharing your opinions on the relative importance of the Altivec information you just posted for MorphOS users?

Any insight regarding the possibility of any e6500 core processors being put onto a board that might be a possible future candidate to port MorphOS3.x to?

> would you mind sharing your opinions on the relative importance of the
> Altivec information you just posted for MorphOS users?

I'm not so sure about the importance for MorphOS users, but that's okay I guess since this is the "General Discussion" board where relevance for MorphOS is not obligatory in any way.

> Any insight regarding the possibility of any e6500 core processors being put onto
> a board that might be a possible future candidate to port MorphOS3.x to?

No, I don't possess any insight of such kind other than A-Eon's public indication to commission Varisys to develop and build boards with QorIQ chips as successors to Nemo/X1000, and Varisys' publicly declared commitment to the QorIQ line of Power Architecture chips.

Addendum:

> I'm going to tell how I perceive this "quite a story" came along in
> chronological order:
> [...]
> 4. Apple calls P.A.Semi's existing customers for final PA6T
> orders as the chip is going to be discontinued. Varisys informs
> A-Eon about this call.
> 5. A-Eon asks Varisys to place an order for an (unknown to us)
> amount of PA6T chips. Varisys agrees.
> 6. Varisys orders the chips from Apple. The chips arrive at Varisys.
> 7. A-Eon in turn purchases those chips from Varisys, effectively
> rendering Varisys A-Eon's CPU supplier (the chips remain at Varisys,
> though, for obvious reasons). As part of this supply agreement
> between Varisys and A-Eon, Varisys demands an NDA* to be signed.

Taking into account Trevor Dickinson's most recent statement about A-Eon/Varisys now having to pay double the price for the PA6T chips, there must be something to the story that I missed. Maybe the (unknown to us) amount of PA6T chips they purchased from Apple's "final call" has been depleted and they now have to source further remnants from other, much more expensive sources?

Update:

> there's an interesting tweet by IBM from June 2011 which seems to confirm that
> the Wii U actually uses the very same POWER7 *chip* (not just the same core) as
> IBM's Watson computer, which would mean an eight-core POWER7 chip. I find that
> very hard to believe.

If the recent information about Wii U's CPU being a three-core chip is true, this would mean that IBM purposely spread false information in June 2011. There's not even a POWER7 chip with 3 cores* (4 cores being the smallest variant).
And from last month two other tweets from the same IBM twitter account that, citing an old Engadget article, suddenly read way more vague and contradict the older tweet (same chip as in Watson vs. custom chip):

http://twitter.com/IBMWatson/status/231902074890248192
http://twitter.com/IBMWatson/status/240241146213842944


* Edit:
In http://www.redbooks.ibm.com/redbooks/pdfs/sg248003.pdf (pages 20 ("6"), 22 ("8") and 27 ("13")) it is revealed that "C1" is IBM's name for the CPU cores in the POWER7 chip.

[ Edited by Andreas_Wolf 07.01.2013 - 17:42 ]

All is legend aobut this machine as Camelot I don't see someone and only I know one case of X1000 owner!

> only I know one case of X1000 owner!

Have a look then at the place where they're gathering:

http://forum.hyperion-entertainment.biz/viewforum.php?f=33

Andreas_Wolf,
Quote:


This is marketing you are talking about. The terms chip and core will be interchangeable!

They would't want all the capabilities of the POWER7 cores so it could be 3 stripped back cores.

> This is marketing you are talking about.

Yes, of course. But also marketing can include false information and even lies. That doesn't make it venial just because it's marketing.

> The terms chip and core will be interchangeable!

Not to anyone who knows a little about those things, like the people questioning IBM and getting those idiotic replies in return.

> They would't want all the capabilities of the POWER7 cores

...or chips.

> so it could be 3 stripped back cores.

Yes, it could be, like the PPC970 has 1 stripped back POWER4 core. But I would also have objected to statements like "G5 Mac uses same POWER4 chips". It's simply misleading. And we'll see how much POWER7 "processor tech" the Wii U CPU will really pack apart from the eDRAM.

No I'm Sam fan, sorry.

>>> only I know one case of X1000 owner!

>> Have a look then at the place where they're gathering:
>> http://forum.hyperion-entertainment.biz/viewforum.php?f=33

> No I'm Sam fan, sorry.

So what? Even Sam fans can view Hyperion's X1000 support forum and see that there's more than just one X1000 owner out there :-)

Yep, I only know one X1000 owner myself and that would be David (hope your doing well Dave).

Andreas, I need to keep up on your postings.

These last few have been very education.

BTW - What's your guess as to Varisys' processor of choice?
I'm thinking something based on the e6500.

> What's your guess as to Varisys' processor of choice?
> I'm thinking something based on the e6500.

If you're talking about the successor to the X1000 here (whose processor would be A-Eon's choice rather than its contractor's), then my opinion has not changed from what I said in December 2011, which was:

"A-Eon already hinted at Freescale's QorIQ P4 and P5 chips for future hardware. In my opinion it would be better for them to wait for the availability of the AltiVec-enabled QorIQ AMP (= T series) chips, at least for the X1000 successor, as even the top end P series chips are only a little better performing than the PA6T, if at all, and they lack AltiVec."

Since I made this statement,
1. the QorIQ P series got enhanced from 2.2 GHz (P5010/P5020) to 2.4 GHz (P5021/P5040),
2. benchmark results have shown the PA6T to be underperforming compared to the expectations I had when I said the top end QorIQ P series chips were only a little better performing,
3. it was revealed that the e6500 core will be limited to QorIQ T2 through T5 chips (as T1 has only e5500).

So it may be that already the P5021/P5040 would be a significant step up from the PA6T, but I still believe it's better to use T4 or even wait for T5 due to them being AltiVec-enabled. The flipside is that real development based on T series chips can not start yet due to lack of sample availability (T4 samples were announced for mid-2012, but I'm not sure they're there already), while with P5 Varisys may have started work as soon as the Nemo v2.1 design was finalized (which was over a year ago).
Leaving AltiVec aside, a DMIPS per core/thread comparison between P5 and T4:
P5: 3.0 DMIPS/MHz * 2400 MHz = 7200 DMIPS
T4: 3.3 DMIPS/MHz * 1800 MHz = 5940 DMIPS
So from that perspective, the P5 has a 20% performance advantage over the T4. Let's see how fast Freescale will get the T5 (announced are 2.5 GHz, i.e. 8250 DMIPS per core and thus 15% higher Dhrystone performance per core than P5).

Yes, I am still here Jim, and I just moved the Nemo2.1 motherboard and other components from my damaged in transit X1000 Boing Ball case, into the undamaged replacement case that AmigaKit sent to me. I have posted a picture of my custom paint job on the new case in a thread over at AW.net.

http://amigaworld.net/modules/newbb/viewtopic.php?mode=viewtopic&topic_id=36318&forum=33&start=0&viewmode=flat&order=0

What ever CPU Trevor and the engineers at Varisys decide to use for the next A-Eon motherboard design, I hope that a complete computer can be built and sold for about half the cost (or less) of what they are forced to charge for the current X1000.

I also hope that it will be a design that appeals to the MorphOS Dev. Team, so a port might be possible. Then the Pegasos2 won't be the only computer capable of running both OS4.x and MorphOS3.x.

It is doubtful that this will happen, but I can still hope for it to occur.

[ Edited by amigadave 02.09.2012 - 14:49 ]

Andreas_Wolf,
"Leaving AltiVec aside, a DMIPS per core/thread comparison between P5 and T4:
P5: 3.0 DMIPS/MHz * 2400 MHz = 7200 DMIPS
T4: 3.3 DMIPS/MHz * 1800 MHz = 5940 DMIPS"

Freescale insists that e6500 delivers 6.0DMIPS/MHz.
But we agree that it's only when hyperthreading (SMP) is used?

Whatever the next high end A1 CPU will be, it is clear that without SMP there is no real way forward.

btw. To me it seems that T2080 could be pretty good PA6T replacement.
and for some 3000EUR T4240 & 129600DMIPS would be "ok".

[ Edited by KimmoK 03.09.2012 - 14:02 ]

>> T4: 3.3 DMIPS/MHz * 1800 MHz = 5940 DMIPS

> Freescale insists that e6500 delivers 6.0DMIPS/MHz.
> But we agree that it's only when hyperthreading (SMP) is used?

Yes, as this is exactly what Freescale says. In June at FTF, they revealed that a single e6500 thread delivers 3.3 DMIPS/MHz. See there:

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7001&start=743

And due to the fact that a thread (or 'virtual core' in Freescale speak) is not a full core it's only logical that a single thread running delivers better than half the performance of both threads running in SMT mode.

> To me it seems that T2080 could be pretty good PA6T replacement.

Yes, from a desktop computing point of view, the only drawback of the T2080 compared to the T4240/T4160 is the lower number of SerDes lanes available (2x8 vs. 2x16/2x12). On the other hand, the T2080 should be way cheaper than the T4 chips. And we should take into account that the bandwidth per SerDes lane of the QorIQ T2/T4 is quadruple that of PA6T's bandwidth per SerDes lane.

Reminder:

> Hyperionmp says:
> "The way in which it will be implemented however is already clearly defined
> and was subject to peer review by other developers. Obstacles to an
> efficient implementation were removed (e.g. the use of Forbid) and replaced
> in many OS components over the years (e.g. DOS). The foundation for
> SMP support was put in place, a clear picture exists what needs to be done
> to accomplish it and how. I'm willing to take a bet that it won't take 2 years ;)"
> http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=34171&forum=33&start=40#627520

Halftime :-)

Don't forget the last sentence in that posting.

Quote:

That gives them an out to extend when SMP will be finished, by saying that they have been working on anything else that is "more desireable".

As an owner of an X1000, I am hoping that they will finish their implementation of OS4.x SMP, so I can take advantage of both cores on my PA6T CPU.

[ Edited by amigadave 04.09.2012 - 01:32 ]

> the last sentence in that posting [...] gives them an out to extend
> when SMP will be finished, by saying that they have been working on
> anything else that is "more desireable".

I understand "something better" in this context as meaning "something better for leveraging the yet unused core(s) than SMP" (like for instance bound multiprocessing (BMP), which I'd say isn't really better than SMP but might be easier to implement). But maybe you're right and he literally means "anything else", which might even be a new icon set ;-)

Another thing in the way could be a (400mhz) netbook that needs heavy tweaking in SW to make it usable...

@KimmoK,
Quote:

Exactly what I meant.

They could use any excuse for the delay in implementing SMP for OS4.x.

It won't bother me, I have not worried about when features of OS4.x are released, or when OS4.2 will be finished, or even what OS4.2 will include when it is released. Just like I don't get worried about when the next version of MorphOS will be finished and what it will include. I do have some preferences about what I would like to see included in the next version of MorphOS3.x, or OS4.x, but I have no idea if what I want to see included is even being worked on yet.

I don't understand users who complain about what should be included next, or when a release should be finished. Even if I have things I wish were already finished and released, there is no point in getting worked up about any of it, so I just try to enjoy what is released now.

When OS4.2 gets here, I will enjoy what ever it includes, as long as it is an improvement over what I have now. It is only when new OS versions seem to go backwards by breaking things in the OS that I use often, or becoming noticeably slower that would cause me to lose interest, like MacOSX10.4.11 to MacOSX10.5 seemed to do in a few ways. Unfortunately, there are many MacOSX programs that only run on MacOSX10.5 and will not run on 10.4.

[ Edited by amigadave 05.09.2012 - 15:11 ]

>"bound multiprocessing"

Had to doa little research on the one.
Luckily there were some fairly easy to understand document on QNX support sites.
Interesting idea.

Update:

>> Is there a chance to order a X1000 in the future?

> I very much think so, else the "First Contact" systems
> should better be named "Last Contact" systems ;-)

"The current X1000 batch (Third batch) may be the last production acording to Trevor. A new more commercially viable design to follow."
http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=36690&forum=2&start=20#685471

If that is true the current 2nd "First Contact" batch (= 3rd batch in total) is really the "Last Contact" batch.

On the other hand, Trevor wrote:

"Additional production runs will be scheduled should demand continue to exceed the supply."
http://blog.a-eon.biz/blog/?p=1252

Edit:
The video of Trevor's AmiWest 2012 presentation (direct link, Youtube) confirms what has been reported from the show:

"We're on the last production run now. [...] We're on our 3rd production run, which will probably be our last production run. [...] This is the last batch."

[ Edited by Andreas_Wolf 20.11.2012 - 23:19 ]

Andreas_Wolf,
Quote:

Yeah, bring on the Qorlq based board!