Andreas, I didn't respond immediately to this because I wanted to avoid a protracted argument over opinions.
We both know the PPE core of the Cell is a little weak, but that will not be a problem with its successors (which will feature out of order execution pipelines).
While I have given up on the idea of asymmetrical multi-core processors or the SPEs, their value and real world performance potential is debatable. And whether you consider the additional programming considerations necessary to harness them "more invilved" or very significant, it does require consideration.
This is where Microsoft's use of multiple identical cores on the Xenon may make more sense than the odd combination used in the Cell. Code is uniform requires no more consideration for the architecture then it be threaded.

I don't mean to slight minator or any of the other Cell "experts" (although I have given you my definition for "expert"). But, while I respect IBM's engineering prowess, I'm not sure they've proven their case on the utility of this approach.

@ minator,

>The same one: OpenCL

Really? I didn't know that and I think that's very cool.
OK, I was wrong and I'm glad to know that as this is something significant.
Suddenly CPUs with integrated GPUs and a Power design incorporating SPEs begin to have a common utility that I find VERY appealing.
Thanks minator.

God, I love this forum.
I get fascinating, useful answers and information all the time.

And yes Andreas, you were the one that pointed out the IBM programming examples that left me questioning the overall complexity of Cell programming requirements.
I've never denied that you are the best resource on the planet for such links.
Why do you think I value your input so much?

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Of course you do know the OpenCL programming model is more complex than Cell....

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The MS approach proved very successful at the beginning of the current console cycle because it was easier to get things up and running.

However, to get the maximum performance out of it is no easier than Cell. To get maximum performance out of *any* processor requires detailed knowledge of its internals. The tricks you use to get that performance out of Cell are exactly the same tricks you use to get performance out of any processor.

In fact, it might be more difficult to get maximum performance from Xenon. The SPEs are deterministic, you know exactly what data is in the local memory. You don't know what is in a cache.

Even if you do manage to get maximum performance out of Xenon, you still only have half the performance of Cell.

It's a trade-off. Cell is more complex to program (Note: I never said it was simple) but in return for more work you get more performance. The design also has a lot to do with power consumption, there is no out-of-order because it would have required far too much power. The SPEs are very simple (i.e. they are true RISC processors) because any more complexity would make them too big and to hot.

Would it have been better if they had made PPC SPEs? for the PS3 no. For market acceptance beyond the PS3, almost certainly yes.

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I was going by brand, not ISA

> I was going by brand, not ISA

And here I was foolish enough to think we were having a *technical* discussion. My bad ;-)

> the PPE core of the Cell is a little weak, but that will not be a problem
> with its successors (which will feature out of order execution pipelines).

You know that Cell's successors (which ones in particular?) will feature out-of-order execution? How do you know?

> you are the best resource on the planet for such links.

Planet? Wow. MorphZone would have been kudos enough, thanks ;-)

>You know that Cell's successors (which ones in particular?) will feature out-of-order execution? How do you know?

Just an assumption that the next generation of Power processors would feature out of order execution.

>>you are the best resource on the planet for such links.

>Planet? Wow. MorphZone would have been kudos enough, thanks

Of course the whole planet. This is the world wide web after all.

> Just an assumption that the next generation of Power
> processors would feature out of order execution.

Ah okay, so you're referring to POWER8 with SPEs then. I wasn't sure if you actually meant this or rather the rumoured new Cell in the PS4, which I suspect would be another thing than the POWER8 and presumably in-order again. But specifics on the PS4's CPU are all just rumours yet anyway whereas we definitely know that POWER8 is in the works and that it will probably sport SPE technology. Like you I think POWER8 will likely feature out-of-order execution but I couldn't find any definite information on this so far.

Your posts contained the first speculation about Power8 featuring SPEs that I'd seen, but it does look like this is going to happen.
The PS4 is a complete unknown since Sony doesn't want the public to focus on that yet. I think they're afraid it would hurt PS3 sales.

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Not really, IBM have pretty much said this themselves.

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Sony are keeping quiet but there's been rumours about a 16 SPE+2 PPE version.
Sony have said they want to keep costs down and give an architecture change would be a huge cost I take that to confirm Cell again.

As to whether the new PPE is Out-of-Order is another question altogether. They should be able to get the power down by now, but it's really a question of if it provides that much benefit to the target applications.

>Sony are keeping quiet but there's been rumours about a 16 SPE+2 PPE version.

That would make for an interesting design, basically doubling the Cell BE.
Considering the finer process IBM is making the Cell on now it could be just that (two Cells on one die).

> Not really, IBM have pretty much said this themselves.

You missed the "that I'd seen" part of Jim's post it seems :-) Obviously my posting where I reported what an IBM executive had told in an interview some days before was where he read it first.

Yes, I'd not heard about the interview with Jai Menon before that.
And after the cancellation of the PowerXCell8i, it was welcomed news.

> the cancellation of the PowerXCell8i

Err, PowerXCell 8i is there. You mean PowerXCell 32ii and PowerXCell 32iv, right?

Sorry, bad cut and paste.
Did I at least get the name of the CTO correct?

> Did I at least get the name of the CTO correct?

I think so ;-)

> Your posts contained the first speculation about Power8 featuring SPEs
> that I'd seen, but it does look like this is going to happen.

There're dissenting opinions as well:

"IBM [...] hinted that in the future its commercial-grade Power chips would incorporate many of the functions of the Cell chips. This [...] could happen with Power7+ or Power8 chips -- or, more likely, not at all. It seems far more likely that IBM will now focus on hybrid CPU-GPU combinations for certain HPC customers"
http://www.theregister.co.uk/2011/06/28/ibm_kills_qs22_blade/

@ Andreas_Wolf

Speculation. I bet we don't get a solid answer about this for a year or more.

> I bet we don't get a solid answer about this for a year or more.

First solid information on POWER7 preceded its official release by 1.5 years. Going by that, 1 year from now plus 1.5 more years would mean early 2014 for POWER8 release. But as we know that POWER8 is scheduled for 2013 (and rather early than late that year), solid information may be imminent ;-)

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It's not quite the same.

As I understand it, on ARM the problem would be intermixing big endian code (68K, PPC) with little endian code (ARM). In both cases the data is all big-endian.

On IA32 everything is little-endian, code and data.


What I had suggested is essentially 2 A-Boxes. One includes a PPC emulator to run PPC and 68K code.

The second A-Box (B-Box?) would only run natively compiled ARM code. No intermixing.


This has a big advantage for moving things forward:
If you are building a new box that you know requires at least a re-compile, you could also add other conditions. e.g. Forbid() could be either be ignored or forbidden (pardon the pun).

You could also put down plans for moving towards things like full memory protection and multi-processing.

I'm not sure how you'd go about this but you could possibly do it with proxies. The app would talk to the proxy thinking it was the OS. The Proxy then does the interaction with the OS.

Then, you build a "C-Box" with memory protection etc. In this box your app still speaks to the proxy but this time it doesn't write directly into kernel memory as the Amiga does.

I don't know how easy or difficult that would be in practice but it would give you an ordered transition that would allow you to migrate today's software into a rather more modern environment. A sudden leap is not likely to work.

There would be a cost to using proxies of course but given how much ARM's performance will shoot up over the next couple of years it's not something you're likely to even notice.

Is MorphOS going the arm route?. Whatever route it chooses, i hope it gets powerful hardware.

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No idea, but that's the rumour.
They have to go somewhere after the G5.

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I think that's a given whatever they do.

The g5 route is interesting. I tried to get a dual g5 on ebay but got overbid on the last minute, damn!.
Still looking for a good deal also on a g4 tower.
The problem, is that the arm processors i know, aren't powerful enough for desktop, only for phone/tablet use. Are out there more powerful arm cpus?

> The problem, is that the arm processors i know, aren't
> powerful enough for desktop, only for phone/tablet use.
> Are out there more powerful arm cpus?

More powerful than the ones you know? Nobody can answer this as long as you don't list the ARM CPUs that you know ;-)
In any case, the most powerful one currently still seems to be the one that I mentioned back in January in the last sentence of that posting:

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7001&start=525

Latest information on that:
http://www.youtube.com/watch?v=3ibShHKLjMM
http://www.youtube.com/watch?v=9yq9TW6xQOw

At 1.6 GHz and below it's still a chip intended mainly for mobile computing including notebook/netbook, not only phone/tablet. In the first video however they also show an AIO computer prototype based on it, and in the second video they call this prototype a reference design. So from that I conclude that they also intend to target general desktop computing with this chip, presumably with the 2.0 GHz version.
That said there seems to be a little confusion regarding the 2.0 GHz version and laptops. In the first video it's said that the 2.0 GHz chip will be used in laptops because its power consumption is too much for mobile devices. Some might say that a laptop is a mobile device as well...