Yokemate of Keyboards
Posts: 11438 from 2003/5/22
> First test chip tape-out (180nm) is claimed to be a mere 5 days away
Took a little longer: https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/
The Libre-SOC test ASIC is claimed to be "implementing a fixed-point subset of the v3.0B OpenPOWER ISA
", which is strange considering that compliancy subsets were introduced only with v3.0C of the ISA
. There are no subsets in v3.0 or v3.0B.
Fun fact: "The Cell Library used, FlexLib, […] was developed by Staf Verhaegen of Chips4Makers […].
" This happens to be MorphZone member Fats
And of course, also this significant event doesn't come without some dubious statements
from the project lead:
"Libre-SOC […] is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years.
Well, during the last 12 years, Freescale/NXP has released more than a dozen different e200-based ASIC products (not counting variants of those), the most recent one being the 16nm S32R294
released this year. Also, the entire QorIQ T family and most of the QorIQ P family are younger than 12 years. Would be interesting to know which 2009-ish non-IBM Power ISA ASIC with IBM-independent microarchitecture he's referring to here in particular, and why he doesn't accept all those later NXP/Freescale ASICs to meet his mentioned criteria.
"they had to go through some serrioous review to get OpenPOWER out the door and into the OPF, ironically it's been ongoing for something like a decade, long before RV existed.
To contrast this with the timeline as it took place in the real world:
2010: RISC-V project started
2011: first version of RISC-V ISA released
2013: OpenPOWER Foundation founded (as OpenPOWER Consortium)
2015: RISC-V Foundation founded, Power ISA v3.0 released
Edit: more of this nonsense[ Edited by Andreas_Wolf 20.07.2021 - 10:32 ]