Open Power
  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    Addendum:

    > Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

    Still no link to the spec, but some mention of Power ISA 3.0C in slides from ICS in June 2020 (page 2):

    "April 2020 – POWER ISA 3.0c [...]
    - Same as POWER ISA 3.0b except for
    • Compliancy Subsets
    • Custom Extension Space (Sandbox)
    • SMF Feature
    "

    (further mentions on pages 3 and 6)

    Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg
  • »09.09.20 - 08:48
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  • Order of the Butterfly
    Order of the Butterfly
    ernsteiswuerfel
    Posts: 438 from 2015/6/18
    From: Funeralopolis
    Quote:

    Andreas_Wolf schrieb:
    Okay, not the 405, but the pre-existing yet until now secret A2O, which compared to the well-known in-order A2I added out-of-order execution at the cost of being reduced from SMT4 to SMT2.

    Not too shabby for an embedded core. ;-) And certainly more advanced than the 405 (or the 440 of the Sam460 ex), being 32bit Power ISA v.2.03 cores (roughly POWER5), where the A2O is 64bit Power ISA v.2.07 (roughly POWER8).

    But apart from being ISA v.2.07 compatible it does not seem to feature a SIMD vector unit (Altivex, VSX) nor an MMU? (klick)
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  • »19.09.20 - 00:43
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    > the 405 (or the 440 [...]), being [...] Power ISA v.2.03 cores (roughly
    > POWER5), where the A2O is [...] Power ISA v.2.07 (roughly POWER8).

    I really don't get this fixation on Power ISA revisions. The PPC405 or PPC440 are nothing like the POWER5+, even if both are Power ISA v2.03. And likewise, the A2O is nothing like the POWER8, even if both are Power ISA v2.07. The option-based way the Power ISA (except v3.0/v3.0B, which gave up on optionality) spec compliancy works (v2: sets of categories defined by Books; v3.0C/v3.1: compliancy subsets) makes the ISA revision mostly irrelevant for comparison of microarchitectures/cores. To illustrate my point, see if you can find any new feature in the v2.07 A2O compared to the v2.06 A2I that was added in Power ISA v2.07.
    There's one extremely relevant thing with Power ISA versions, namely the turning point that IBM created with Power ISA v3.0 in 2015 (see comments #88, #163, #165, #167), which prevents Power ISA v2 Book III-E cores from being used commercially (i.e. hard core, ASIC) under the royalty-free OpenPOWER v3.0C or v3.1 licenses. Thus, the v2.06/2.07 A2I and A2O cores cannot be used commercially under the license by 3rd parties unless those cores be upgraded to ISA v3.0C or v3.1 level, which includes, among other things, replacing the embedded supervisor instructions (from Book III-E of Power ISA v2) by non-embedded ("server") supervisor instructions (from Book III-S of Power ISA v2, or from Book III of Power ISA v3 or pre-v2.03 PowerPC ISA). This is quite an effort.
    As it stands, the commercial usability of A2I/A2O in the OpenPOWER context is not really there. IBM could have contributed not just Power ISA v3.0C and v3.1 but also old Power ISA v2 revisions to the OpenPOWER Foundation for 3rd party use, but they decided not to do this and I'm sure they have their reasons for this decision. Btw, IBM can as well open-source any of its Power ISA v2 Book III-S cores, like POWER5+ to POWER8, or any of its old pre-v2.03 PowerPC cores, like 40x (the 440 being the first IBM core with Book-E extensions), 6xx, 7xx, 970, Cell PPU (probably subject to consent by Sony and Toshiba, though), POWER3 to POWER5. Anything from that list is more compliant with Power ISA v3 than A2I/A2O is, and I'm still hopeful with regard to this.

    > it does not seem to feature a SIMD vector unit [...] nor an MMU?

    No SIMD, but basic MMU is there.


    Edit: changed wording

    [ Edited by Andreas_Wolf 07.03.2021 - 21:41 ]
  • »19.09.20 - 04:43
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  • Order of the Butterfly
    Order of the Butterfly
    ernsteiswuerfel
    Posts: 438 from 2015/6/18
    From: Funeralopolis
    Quote:

    Andreas_Wolf schrieb:
    The PPC405 or PPC440 are nothing like the POWER5+, even if both are Power ISA v2.03. And likewise, the A2O is nothing like the POWER8, even if both are Power ISA v2.07. The modular way the Power ISA spec compliancy works (Books with optional parts and optional feature sets) makes the ISA revision mostly irrelevant for comparison of microarchitectures/cores.

    So CPUs compliant to the same ISA don't understand the same instructions? Seems a bit more complicated than I thought...
    Talos II. [Gentoo Linux] | PMac G5 11,2. PMac G4 3,6. PBook G4 5,8. [MorphOS 3.15 / Void Linux / Gentoo Linux] | Vampire V4 SA [ApolloOS / Amiga OS 3.2]
  • »19.09.20 - 23:49
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    > CPUs compliant to the same ISA don't understand the same instructions?

    Exactly, the Power ISA revision usually tells nothing about the supported instructions of the microarchitecture/core declared compliant with the respective Power ISA revision. With each new Power ISA revision, new optional features/instructions were added (exception: Power ISA v3.0 which killed entire Book III-E and Book VLE). Every new Power core was simply declared compliant with the ISA revision that was recent at time of release, no matter if it supported the new optional instructions or not. Usually, the big IBM POWER processors were the ones that supported the new instructions and that the new ISA revision was released for in the first place. This way of assigning ISA revisions to cores has been legit as new instructions have always been optional. That's why a core declared compliant with a certain ISA revision is automatically compliant with all follow-up revisions (exception again: Power ISA v3.0).
    This way, the very same ISA revisions are shared by
    - cores with FPU and without
    - cores with MMU and without
    - Book III-S cores and Book III-E cores
    - Book III-E cores with SPE and Book III-E cores without
    - cores with VLE and cores without
    - VLE cores with Book I-III instructions and VLE cores without
    - cores with SIMD and cores without
    - SIMD cores with VSX and SIMD cores without
    - cores with AltiVec/VMX in both endians and cores with AltiVec/VMX only in big-endian
    - 32 bit-only cores, 64 bit-only cores and 32/64-bit cores
    - cores with decimal FP and cores without
    - cores with transactional memory and cores without

    These are just the most obvious instruction set differences. And to give you the most extreme example, both the e200z0 and the POWER5+ implement Power ISA v2.03, yet they do not have even one single instruction in common.

    > Seems a bit more complicated than I thought

    This graph is quite okay, but it has a major flaw: it implies that Power ISA v3.0 and above still contain Book III-E and Book VLE, which they do not. (As minor flaws, it falsely implies that Power ISA v3.0 and above have been released by Power.org, and it's missing Power ISA v3.0C.)
  • »20.09.20 - 01:36
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    Addendum:

    >> Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

    > some mention of Power ISA 3.0C in slides from ICS in June 2020
    > (page 2): [...] (further mentions on pages 3 and 6)
    > Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg

    Revised presentation from OpenPOWER Summit NA 2020:
    https://www.youtube.com/watch?v=ZGvEpd4vNK0

    Inexplicably, the occurences of "3.0c"/"3.0C" on pages 2/3 got replaced by "3.0", which is of course plain wrong as neither has Power ISA v3.0 from 2015 (or v3.0B from 2017) been contributed to the OpenPOWER Foundation nor does v3.0 (or v3.0B) have any compliancy subsets. Both things started only with v3.0C/3.1.
    These changes to the slides must have been made deliberately. What the heck is going on there?


    Edit: "V3.0C" mentioned in https://www.youtube.com/watch?v=SO8a8zcAiZc (at 13:00 and 20:04) and https://video.fosdem.org/2021/D.power/microwatt_grows_up.mp4 / https://video.fosdem.org/2021/D.power/microwatt_grows_up.webm (at 5:00 and 13:33)
    (Btw, funny how Paul Mackerras in the first video at 11:45 claims that the ISA renaming in 2006 from PowerPC ISA (v2.02) to Power ISA (v2.03) by Power.org happened because Freescale allegedly had very much stopped using the ISA so that it was pretty much just about the IBM POWER line of server CPUs at that time (and in the second video at 4:18 that it happened because IBM allegedly was the only company using the ISA or making any new CPUs with it), when in fact the opposite is true, namely that the renaming represented the incorporation of the Book-E extensions (implemented by IBM PPC440/PPC460 and Freescale e200/e500 back then, which are embedded class and thus as un-POWER as possible) into the official ISA specification.)

    [ Edited by Andreas_Wolf 18.02.2021 - 22:03 ]
  • »22.09.20 - 22:36
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    Update:

    > Schedule:
    > - 2020 "shuttle smoketest" tapeout of 180nm (TSMC) embedded-class
    > single-core chip, OOO, pipelined
    > - 2021 commercial single-core or quad-core (information are conflicting
    > here) chip with GPU
    > - 2022 commercial 0.8-1.0 GHz quad-core chip with GPU (25-50 GFLOPS),
    > 1080p25 video, VPU, DDR SDRAM controller, SERDES, UART, LPC,
    > JTAG, GPIO, 3 watts power consumption

    Most recent Libre-SOC schedule from the mission statement:
    - 12/2020: "demo" of 180nm single-core dual-issue 64-bit QFP chip, saleable in the "Embedded" space
    - later: 800 MHz quad-core dual-issue SoC with 4-wide FP32, hybrid CPU/GPU/VPU
    - even later: addition of an ML inference core


    Edit:

    Even more recent schedule from the business plan:
    - Q2/2021: 130nm test chip (Google/SkyWater MPW shuttle program)
    - Q4/2021: 180nm QFP SoC
    - Q2/2022: 28nm or 20nm quad-core SoC for BMC and SBC use; USB-C and PCIe host/device controllers, i.e. also usable as peripheral GPU
    - Q2/2023: then-latest process node; targetting smartphones, netbooks, tablets, IoT and IPTV

    Seems the previous schedule got delayed by some months.

    [ Edited by Andreas_Wolf 28.12.2020 - 12:02 ]
  • »07.12.20 - 08:41
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    Update:

    > ChipEleven: https://chipeleven.com
    > [...]
    > Features acc. to sources:
    > - market-ready by spring 2022
    > - 3 watts power budget
    > - PythonWatt quad-core: pipelined, 8-stage, SMP, 1.5 GHz
    > - Mali GPU, 1080p60 video
    > - DDR4, PCIe, IPMI, LPC, USB2, GbE

    Some additions and changes according to website:
    - market-ready by spring 2023 (i.e. a year delayed)
    - SoC name: SuperPOWER
    - single-issue, out-of-order execution core
    - Mali-G77 GPU
  • »06.01.21 - 22:54
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    Update:

    > schedule from the business plan:
    > - Q2/2021: 130nm test chip (Google/SkyWater MPW shuttle program)
    > - Q4/2021: 180nm QFP SoC
    > - Q2/2022: 28nm or 20nm quad-core SoC for BMC and SBC use; USB-C and
    > PCIe host/device controllers, i.e. also usable as peripheral GPU
    > - Q2/2023: then-latest process node; targetting smartphones, netbooks, tablets,
    > IoT and IPTV

    Most recent schedule update*:
    - 202X: 300 MHz single-core
    - 202X+2: quad-core
    - 202X+4: 8-core
    - 202X+6: 64-core

    (* The notion that VSX is 15 years old is incorrect. VSX was first specified in Power ISA v2.06 in 2009 and first implemented in POWER7 in 2010.)


    Edit: "Quad and 8 1.5+ ghz on the roadmap over the next 3 years"

    [ Edited by Andreas_Wolf 20.07.2021 - 01:47 ]
  • »15.04.21 - 21:34
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  • Order of the Butterfly
    Order of the Butterfly
    ernsteiswuerfel
    Posts: 438 from 2015/6/18
    From: Funeralopolis
    Ah, finally we are getting somewhere! At least the 'quad-core as SBC' looks interesting. But we'll have to wait and see how this translates to available products in 202X+2. ;-)

    @Andreas_Wolf: Thanks for your continuous updates! Looking at the schedule update you posted I gather that VMX/VSX will not be implemented (too much work?) for the time being?
    Talos II. [Gentoo Linux] | PMac G5 11,2. PMac G4 3,6. PBook G4 5,8. [MorphOS 3.15 / Void Linux / Gentoo Linux] | Vampire V4 SA [ApolloOS / Amiga OS 3.2]
  • »15.04.21 - 22:30
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  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 11438 from 2003/5/22
    From: Germany
    > I gather that VMX/VSX will not be implemented (too much work?)
    > for the time being?

    Yes, correct. Their long-term plan is however to not implement VMX/VSX ever but instead somehow convince IBM and the OpenPOWER Foundation to abandon VSX in favour of Libre-SOC's non-SIMD SimpleV (or Simple-V, seems they can't decide on one spelling variant) vector augmentation.
  • »16.04.21 - 00:03
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