Addendum:

>> Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

> some mention of Power ISA 3.0C in slides from ICS in June 2020
> (page 2): [...] (further mentions on pages 3 and 6)
> Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg

Revised presentation from OpenPOWER Summit NA 2020:
https://www.youtube.com/watch?v=ZGvEpd4vNK0

Inexplicably, the occurences of "3.0c"/"3.0C" on pages 2/3 got replaced by "3.0", which is of course plain wrong as neither has Power ISA v3.0 from 2015 (or v3.0B from 2017) been contributed to the OpenPOWER Foundation nor does v3.0 (or v3.0B) have any compliancy subsets. Both things started only with v3.0C/3.1.
These changes to the slides must have been made deliberately. What the heck is going on there?


Edit: "V3.0C" mentioned in https://www.youtube.com/watch?v=SO8a8zcAiZc (at 13:00 and 20:04) and https://video.fosdem.org/2021/D.power/microwatt_grows_up.mp4 / https://video.fosdem.org/2021/D.power/microwatt_grows_up.webm (at 5:00 and 13:33)
(Btw, funny how Paul Mackerras in the first video at 11:45 claims that the ISA renaming in 2006 from PowerPC ISA (v2.02) to Power ISA (v2.03) by Power.org happened because Freescale allegedly had very much stopped using the ISA so that it was pretty much just about the IBM POWER line of server CPUs at that time (and in the second video at 4:18 that it happened because IBM allegedly was the only company using the ISA or making any new CPUs with it), when in fact the opposite is true, namely that the renaming represented the incorporation of the Book-E extensions (implemented by IBM PPC440/PPC460 and Freescale e200/e500 back then, which are embedded class and thus as un-POWER as possible) into the official ISA specification.)

[ Edited by Andreas_Wolf 18.02.2021 - 22:03 ]

Addendum:

> POWER9 AIO postponed to 2020

POWER9′/AIO/Axone cancelled?


Edit: https://twitter.com/RaptorCompSys/status/1330466886069473286

[ Edited by Andreas_Wolf 09.01.2021 - 00:10 ]

> the company behind Libre-SOC:
> https://systemeslibres.org

Systèmes Libres seems to be no more (or never was beside a website) and three months ago turned into ChipEleven:

https://chipeleven.com
https://soc.chipeleven.com
https://wiki.chipeleven.com
https://gitlab.com/chipeleven/soc
https://demoday.create-x.gatech.edu/company/chipeleven/
https://reformventures.com/portfolio
https://www.outlanderlabs.com/portfolio
https://www.pitchbook.com/profiles/company/458176-60
https://vimeo.com/488597617

Features acc. to sources:
- market-ready by spring 2022
- 3 watts power budget
- PythonWatt quad-core: pipelined, 8-stage, SMP, 1.5 GHz
- Mali GPU, 1080p60 video
- DDR4, PCIe, IPMI, LPC, USB2, GbE

As I understand it, PythonWatt is likely derived/forked from Libre-SOC's core (at least two ChipEleven contributors are former Libre-SOC contributors), and the ChipEleven SoC has somewhat different design goals than Libre-SOC, like dedicated vector unit (VSX?) and third-party GPU vs. hybrid CPU+VPU+GPU.

Comments from the Libre-SOC project lead:

"michael etc. do not full comprehend copyright law and took jointly-owned copyrighted material and are slapping an alternative license on it without permission [...]
a quick look shows that michael *might* have started from scratch, including on the power decoder"
https://libre-soc.org/irclog/%23libre-soc.2020-10-27.log.html#t2020-10-27T17:05:41
https://libre-soc.org/irclog/%23libre-soc.2020-10-27.log.html#t2020-10-27T17:27:35

"the founder of chipeleven betraying the trust we placed in them [...] put us behind by at least a year."
https://libre-soc.org/irclog/%23libre-soc.2021-03-29.log.html#t2021-03-29T16:59:11


Edit: added more links
Edit2: added another quote

[ Edited by Andreas_Wolf 24.08.2021 - 22:48 ]

>> he's been repeating this claim to this day.

> That is a bit troubling, isn't it.

He's been at it again:

"Mitch [...] studied the 6600 very early on, recognised its genious, and based the Motorola 68000 on it."
https://www.phoronix.com/forums/forum/hardware/graphics-cards/1207878-libre-soc-still-persevering-to-be-a-hybrid-cpu-gpu-that-s-100-open-source/page17#post1213463

:-(

(On another note, he's not afraid to tell an anecdote of someone in 1995 doing something on a 1998 computer running a factory-installed 2001 OS.)

Update:

> Schedule:
> - 2020 "shuttle smoketest" tapeout of 180nm (TSMC) embedded-class
> single-core chip, OOO, pipelined
> - 2021 commercial single-core or quad-core (information are conflicting
> here) chip with GPU
> - 2022 commercial 0.8-1.0 GHz quad-core chip with GPU (25-50 GFLOPS),
> 1080p25 video, VPU, DDR SDRAM controller, SERDES, UART, LPC,
> JTAG, GPIO, 3 watts power consumption

Most recent Libre-SOC schedule from the mission statement:
- 12/2020: "demo" of 180nm single-core dual-issue 64-bit QFP chip, saleable in the "Embedded" space
- later: 800 MHz quad-core dual-issue SoC with 4-wide FP32, hybrid CPU/GPU/VPU
- even later: addition of an ML inference core


Edit:

Even more recent schedule from the business plan:
- Q2/2021: 130nm test chip (Google/SkyWater MPW shuttle program)
- Q4/2021: 180nm QFP SoC
- Q2/2022: 28nm or 20nm quad-core SoC for BMC and SBC use; USB-C and PCIe host/device controllers, i.e. also usable as peripheral GPU
- Q2/2023: then-latest process node; targetting smartphones, netbooks, tablets, IoT and IPTV

Seems the previous schedule got delayed by some months.

[ Edited by Andreas_Wolf 28.12.2020 - 12:02 ]

Update:

> ChipEleven: https://chipeleven.com
> [...]
> Features acc. to sources:
> - market-ready by spring 2022
> - 3 watts power budget
> - PythonWatt quad-core: pipelined, 8-stage, SMP, 1.5 GHz
> - Mali GPU, 1080p60 video
> - DDR4, PCIe, IPMI, LPC, USB2, GbE

Some additions and changes according to website:
- market-ready by spring 2023 (i.e. a year delayed)
- SoC name: SuperPOWER
- single-issue, out-of-order execution core
- Mali-G77 GPU

Update:

>> Project to be presented at XDC 2020

> Also at OpenPOWER Summit NA 2020

Also at FOSDEM 2021 in February:

https://stands.fosdem.org/stands/the_libresoc_project__a_hybrid_3d_cpu_vpu_gpu/
https://www.fosdem.org/2021/schedule/event/libresocproject/
https://www.fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorisation/

Update:

> the project [...] was approached by Raptor. [...] The use as a board management
> controller for Raptor is just an initial use case for the SoC, if it happens.

Seems the delay in the Libre-SOC project has led Raptor to create Kestrel SoftBMC, their own FPGA-based BMC using Microwatt:

https://twitter.com/RaptorEng/status/1352082171952062468
https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex-boards/-/blob/master/README.md
https://www.phoronix.com/scan.php?page=news_item&px=Raptor-Kestrel

Update:

>> ChipEleven: https://chipeleven.com

> Some additions and changes according to website:
> - market-ready by spring 2023 (i.e. a year delayed)
> - SoC name: SuperPOWER
> - single-issue, out-of-order execution core
> - Mali-G77 GPU

Project presentation: https://www.youtube.com/watch?v=wO5o4MLGtxo

Update:

> Does anybody have a link to that "3.0C" spec?

Finally surfaced: https://wiki.raptorcs.com/w/images/7/70/PowerISA_public.v3.0C.pdf
https://ftp.libre-soc.org/PowerISA_public.v3.0C.pdf

Update:

> Microwatt got big-endian mode, 32-bit mode and an FPU

Microwatt will be manufactured as a 130nm ASIC in the Google/SkyWater MPW shuttle program:

https://openpowerfoundation.org/openpower-foundation-provides-microwatt-for-fabrication-on-skywater-open-pdk-shuttle/

Update:

> schedule from the business plan:
> - Q2/2021: 130nm test chip (Google/SkyWater MPW shuttle program)
> - Q4/2021: 180nm QFP SoC
> - Q2/2022: 28nm or 20nm quad-core SoC for BMC and SBC use; USB-C and
> PCIe host/device controllers, i.e. also usable as peripheral GPU
> - Q2/2023: then-latest process node; targetting smartphones, netbooks, tablets,
> IoT and IPTV

Most recent schedule update*:
- 202X: 300 MHz single-core
- 202X+2: quad-core
- 202X+4: 8-core
- 202X+6: 64-core

(* The notion that VSX is 15 years old is incorrect. VSX was first specified in Power ISA v2.06 in 2009 and first implemented in POWER7 in 2010.)


Edit: "Quad and 8 1.5+ ghz on the roadmap over the next 3 years"

[ Edited by Andreas_Wolf 20.07.2021 - 01:47 ]

Ah, finally we are getting somewhere! At least the 'quad-core as SBC' looks interesting. But we'll have to wait and see how this translates to available products in 202X+2.

@Andreas_Wolf: Thanks for your continuous updates! Looking at the schedule update you posted I gather that VMX/VSX will not be implemented (too much work?) for the time being?

> I gather that VMX/VSX will not be implemented (too much work?)
> for the time being?

Yes, correct. Their long-term plan is however to not implement VMX/VSX ever but instead somehow convince IBM and the OpenPOWER Foundation to abandon VSX in favour of Libre-SOC's non-SIMD SimpleV (or Simple-V, seems they can't decide on one spelling variant) vector augmentation.

Update:

> Project presentation:
> https://www.youtube.com/watch?v=wO5o4MLGtxo

Apparently, ChipEleven has joined the OpenPOWER Foundation:
https://openpowerfoundation.org/members/chipeleven/

Therein, it has become a member of the PowerPi Workgroup:
https://openpowerfoundation.org/groups/powerpi/

"PowerPi" sounds interesting. Alas, no details yet.


Edit: ChipEleven seems to be no longer a member of the PowerPi SIG.
Edit2: ChipEleven no longer OpenPOWER Foundation member
Edit3: ChipEleven listed as "Out of Business" as of "10-Mar-2022".
Edit4: Chip11 Github repository (last commit October 2022: "I don't plan to complete this processor, but rather, plan to do a new implementation in BlueSpec.")
Edit5: MannaChip Github repository ("the POWER3.0 compliant MannaChip processor delivers groundbreaking performance, necessitating minimal intervention on the developer's or user's part.")

[ Edited by Andreas_Wolf 22.09.2024 - 01:44 ]

> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/

Another OpenPOWER SIG, the LibreBMC Workgroup, is apparently planning a new 32-bit big-endian Power ISA core named A2P:

presentation video and slides
presentation video and slides (alternative link)
repository


Edit: added more links

[ Edited by Andreas_Wolf 18.10.2022 - 13:12 ]

> we'll have to wait and see how this translates
> to available products in 202X+2. ;-)

Looks like the RED Semiconductor company has been established for the purpose of commercializing the Libre-SOC technology:

https://www.redsemiconductor.com

First test chip tape-out (180nm) is claimed to be a mere 5 days away:

https://www.redsemiconductor.com/team-build
https://twitter.com/lkcl/status/1400386890923130885


Edit:

"Red Semi […] have a roadmap going single-core, quad-core, 8-core, 16/64-core chiplets, 1024-core supercomputer on substrate using 16/64-core chiplets"
https://libre-soc.org/irclog/%23libre-soc.2021-08-24.log.html#t2021-08-24T15:09:55

[ Edited by Andreas_Wolf 02.09.2022 - 11:45 ]

Lets hope this thing won't turn up in BMCs only...

> Lets hope this thing won't turn up in BMCs only...

Which one? RED's Libre-SOC, ChipEleven's PythonWatt/SuperPOWER, or LibreBMC's A2P? :-)

Any of the above.

Update:

> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/
> "PowerPi" sounds interesting. Alas, no details yet.

Some small details:

"“POWER Pi” a POWER based CPU, Single Board Computer (SBC) including RPi header. Provide platform for devs, hackers and others to easily access POWER based system."
https://www.linkedin.com/pulse/revolutionaries-openpower-momentum-open-source-hardware-venkatesh-a-c-1c

Also there (7:50-8:58):
https://www.youtube.com/watch?v=s_ek-hFhxx8


Edit: added video link

[ Edited by Andreas_Wolf 18.10.2022 - 13:11 ]

> First test chip tape-out (180nm) is claimed to be a mere 5 days away

Took a little longer: https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication//

The Libre-SOC test ASIC is claimed to be "implementing a fixed-point subset of the v3.0B OpenPOWER ISA", which is strange considering that compliancy subsets were introduced only with v3.0C of the ISA. There are no subsets in v3.0 or v3.0B.

Fun fact: "The Cell Library used, FlexLib, […] was developed by Staf Verhaegen of Chips4Makers […]." This happens to be MorphZone member Fats.

And of course, also this significant event doesn't come without some dubious statements from the project lead:

"Libre-SOC […] is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years."
Well, during the last 12 years, Freescale/NXP has released more than a dozen different e200-based ASIC products (not counting variants of those), the most recent one being the 16nm S32R294 released this year. Also, the entire QorIQ T family and most of the QorIQ P family are younger than 12 years. Would be interesting to know which 2009-ish non-IBM Power ISA ASIC with IBM-independent microarchitecture he's referring to here in particular, and why he doesn't accept all those later NXP/Freescale ASICs to meet his mentioned criteria.**

"they had to go through some serrioous review to get OpenPOWER out the door and into the OPF, ironically it's been ongoing for something like a decade, long before RV existed."
To contrast this with the timeline as it took place in the real world:
2010: RISC-V project started
2011: first version of RISC-V ISA released
2013: OpenPOWER Foundation founded (as OpenPOWER Consortium)
2015: RISC-V Foundation founded, Power ISA v3.0 released*,***


* Edit1: more of this nonsense

** Edit2: He tried again and failed once more:
"our […] test ASIC […] is […] the world's first Power ISA 3.0 [ASIC] outside of IBM to reach Silicon in over 12 years."
How can there have been a Power ISA v3.0 ASIC over 12 years ago when Power ISA v3.0 was published only 6 years ago? Which ASIC is he referring to with this statement? Unless I missed something, Libre-SOC is the first Power ISA v3.0+ ASIC outside of IBM ever.

*** Edit3: even more of this nonsense:
"Power ISA [...] pre-dates the RISC-V instruction set by a long way. As does interestingly their intention to open up the ISA, which was initiated about 10 years ago"

[ Edited by Andreas_Wolf 23.06.2024 - 10:03 ]

>> the pre-existing yet until now secret A2O
>> [...]
>> https://openpowerfoundation.org/openpower-foundation-introduces-ibm-hardware-and-software-contributions-at-openpower-summit-2020/
>> https://github.com/openpower-cores/a2o
>> https://git.openpowerfoundation.org/cores/a2o

> Not too shabby for an embedded core.

Ananth, an A2O-based SoC, in development:

https://www.youtube.com/watch?v=FIn1g1jfdVk


Edit: OpenPOWER Summit NA 2021 will have a session on this SoC.
Edit2: Session published.
Edit3: Super Computing 22 OpenPOWER ADG Workshop will have a session on this SoC.

[ Edited by Andreas_Wolf 02.11.2022 - 20:24 ]

Update:

> POWER10

Seems it will be Power10 instead of POWER10:

https://www.rpgpgm.com/2021/07/ibm-updates-power-branding.html
https://www.itjungle.com/2021/08/02/no-more-shouting-the-name-power-well-except-in-our-title-here/
https://www.ibm.com/it-infrastructure/power/power10

…which in my humble opinion is a stupid decision for the following reason:
So far, Power has been (since superseding PowerPC in 2006) the name of the instruction set architecture (ISA), while POWER has been the name of IBM's line of server CPU microarchitectures (POWER1…9, with POWER3…5 implementing PowerPC ISA and POWER5+…9 implementing Power ISA). This means that so far, the (non-)capitalization of the word can be used for distinction between ISA and microarchitecture. With Power10, this will be no more. The ISA and the IBM server CPU microarchitecture will both go by the very same name: Power. So what will be the correct answer to the question whether 440/460/470, A2, e200, e500, e5500, e6500, PA6T or any of the new (soft)cores discussed in this thread are Power? Well, it will depend on what the questioner has in mind, making room for misunderstandings. The correct answer will be 'yes' for Power [ISA], but it will be 'no' for Power [microarchitecture].

Update:

>> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/
>> "PowerPi" sounds interesting. Alas, no details yet.

> Some small details: [...]

Some more details on PowerPi / POWER Pi / POWERπ from OpenPOWER Summit NA 2021:

- SBC with dual-core or quad-core SoC ASIC
- slightly bigger than Raspberry Pi
- 150 USD max

https://www.youtube.com/watch?v=RCSKQoO5AEs (5:59-6:43)
https://www.youtube.com/watch?v=58ZmyKuB-04 (15:49-17:50)