@KimmoK

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What do you mean by "ARM mainstream developers"?

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What phoenixkonsole said above + the fact that Apple has taken a completely different route with the Cyclone design; while most of the others in the ARM mobile market are migrating to whatever next-gen generic cores from ARM that's above their current offering, adding cores to their chips and pumping the clock frequency, Apple has made their own design, and it's a very *wide* chip (á la desktop) that gets (a lot!) more done in less cycles. That's how it can beat quad core chips clocked at ~2GHz, despite it's only a dual core chip running at a mere 1.3GHz.

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You look at the A7 implementation of the Cyclone, and seem to think something along the lines of "Apple really tried it all here, and they didn't reach desktop performance in their A7 chip". Which is silly. What they made was a chip with only 2 cores, only running at 1.3GHz (in the iPhone, 1.4GHz in the iPad), still providing a vast overkill of performance that simply won't be saturated by any (or at least very few) of the current iOS apps.

But what you forget here, is that they in the Cyclone architecture have a real desktop CPU design!

I merged together a three diagrams from anandtech.com into one picture here:

Cyclone_Vs_Haswell.png

(The Cyclone's picture isn't as detailed, since not everything is known yet, much hush hush, and it's also not official but something put together by Anand Lal Shimpi of anandtech.com based upon his research of documentation and his own tests)

This illustrates how *wide* this Cyclone architecture really is, compared to Intel's Haswell architecture.

To quote anandtech:

"Conroe was a very wide machine. It brought us the first 4-wide front end of any x86 micro-architecture, meaning it could fetch and decode up to 4 instructions in parallel. We've seen improvements to the front end since Conroe, but the overall machine width hasn't changed - even with Haswell."

So the Haswell front end decoders can output up to 4 micro-ops per clock, the Cyclone does 6!

The Out-of-Order window in Haswell is 192. The Cyclone matches this. The Branch Mispredict Penalty is also the same for both (14-19 cycles).

The Haswell has 8 ports to execution units, the Cyclone has 9!

Besides, the Cyclone has *twice* the L1 and L2 cache sice (counted per core, though I understand that the Cyclone's L2 cache is shared?)

The way I see it, is that while the A7 implementation seen in the iPhone and iPad may not exactly be a desktop chip (and it wasn't supposed to be either!), the Cyclone Architecture that it is built from certainly is! To me the Cyclone looks very potent, it's cool and energy efficient for its performance, and I really think it would be possible to build CPU's with quad cores (or more) and clock them really high (maybe ~4GHz in a 20nm process) with suitable and powerful active cooling, and then you would have a chip that's definitely would play in Intel's desktop league. And again, the design of this architecture started a few years ago already, I doubt that in-house evolution has stopped over at Apple. More is coming. Probably on a yearly basis like before. And like Anand say at the end of his article "Swift and Cyclone were two tocks in a row by Intel's definition, a third in 3 years would be unusual but not impossible". We'll see...

Look, I'm not claiming that Apple *will* make an ISA change, but I really believe they *could do it*, if they really wanted. I think the Cyclone shows this. They haven't built a desktop CPU yet based on it, probably more because they didn't *want to* rather than because they coudln't, but I think it would be possible. And not in a "distant future" either...