The information therein bring me back to my idea of configurable SerDes lanes. Near the end you find a config table listing no less than 29 different pre-definitions of how to assign the 18 SerDes lanes. Definition '0x14' is the one with the highest amount of lanes dedicated to PCIe: three PCIe controllers used with 4 lanes for each of them, so 12 lanes overall for PCIe. Definition '0x10' assigns only 8 lanes overall to PCIe, but all of them to one single controller. This makes me conclude that my idea was correct that the SerDes lanes on QorIQ are fully configurable like with PA6T, i.e. no hard-wiring involved on a processor level. And I also think that my example configuration of 15 lanes dedicated to PCIe alone is indeed possible, even if it's not part of the pre-definitions. So, to answer the question: it's possible to assign up to 18 SerDes lanes to the PCIe controllers, which makes the processor support no less than 18 PCIe 2.0 lanes (but which would leave you with no Ethernet and no SATA).
