> 4X isn't the most promising connection for a GPU

I don't read this spec as the amount of lanes but as the amount of controllers. Look at the block diagram:

http://www.freescale.com/files/graphic/block_diagram/P5020_BD.jpg

There you have (from left to right) the following controllers:
one 10GbE, five 1GbE, four PCIe, two SRIO, two SATA2, one Debug.

> I wonder if there is any way to utilize the SerDes lanes?

Below the controllers there's a block labelled "18-Lane 5 GHz SerDes". 5 GHz means 500 MB/s throughput per lane, btw. If you count the arrows from the controllers to the SerDes block you'll find that these don't amount to 18 but to only 12. To my mind, this seeming mismatch indicates that the controllers's assignment to the SerDes lanes may be configurable at the board designer's level, just like with the PA6T. So if the board designer thinks that the board could spare for instance the 10GbE port, three 1GbE ports, the two SRIO ports and the Debug port, he can distribute the 18 SerDes lanes across the remaining two 1GbE ports (would use 1 lane), the two SATA2 ports (would use 2 lanes) and would still have 15 lanes at disposal for the four PCIe ports, which could be configured as powering for instance one x8 slot (with x16 physical connector for graphics cards), one x4 slot, one x2 slot and one x1 slot. Let me reiterate that this is PCIe 2.0, so the x8 slot would provide the same bandwidth as the PCIe 1.0 x16 slot on the X1000.
However, that's all assuming my idea that the SerDes lanes are configurable holds true.

Edit:

> All SerDes lanes are assigned functions

You mean they're not configurable? That would be a pity. Do you know how many SerDes lanes are hardwired to which controller in detail? The block diagram isn't really helpful in this regard (see mismatch 12 arrows vs. 18 lanes).

> so the limit is 4x PCIe.

Which would still equal PCIe 1.0 x8 speed ;-)

> The PA6T definitely has an advantage here.

Definitely, provided your above assumption that the SerDes lanes are hardwired to the controllers is correct.

[ Edited by Andreas_Wolf on 2011/3/9 21:42 ]