Yokemate of Keyboards
Posts: 4977 from 2009/1/28
From: Delaware, USA
Quote:amigadave wrote:
Quote:Jim wrote:
Quote:
Andreas_Wolf wrote:
> I am beginning to think the e5500 and e6500 cores may not be reaching
> anything close to their supposed memory bandwidth.
If the cause of the memory performance issue is in the SoC, I think it's in the SoC's 'uncore' (memory controller) rather than its core.
I'd like to see some bandwidth figures for the T10xx CPUs when interfaced with DDR4.
The DDR3 controller used with other e5500 and e6500 cored CPUs does seem to be the issue.
I thought the memory bandwidth and speed for the X1000's PA6T, was one of its few advantages, when compared to the older Apple G4 & G5 computers? Or is the PA6T an exception for e6500 cored CPU's, when it comes to memory bandwidth?
It's probably that I'm not paying attention to this discussion, so I have made an incorrect assumption (again).
Edit: I probably should have changed "memory bandwidth" above, to read/write speed to RAM.
Yep, I think Andreas mentioned this before in response to a similar comment.
The PA6T in the X1000 was produced by PA Semi and does not use a Freescale core.
And yes, it's got better memory bandwidth then a G4 (not sure about the G5 though) as well as the e5500 and e6500 based Socs.
So, even with older DDR2 memory, the X1000's memory controller performs much better than the X5000.
"Never attribute to malice what can more readily explained by incompetence"
