• Jim
  • Yokemate of Keyboards
    Yokemate of Keyboards
    Posts: 4957 from 2009/1/28
    From: Delaware, USA

    Andreas_Wolf wrote:
    > I am beginning to think the e5500 and e6500 cores may not be reaching
    > anything close to their supposed memory bandwidth.

    If the cause of the memory performance issue is in the SoC, I think it's in the SoC's 'uncore' (memory controller) rather than its core.

    I'd like to see some bandwidth figures for the T10xx CPUs when interfaced with DDR4.
    The DDR3 controller used with other e5500 and e6500 cored CPUs does seem to be the issue.
    "Never attribute to malice what can more readily explained by incompetence"
  • »26.01.18 - 01:32