> Another thing that puzzles me regarding Marvell and ARM: > > According to Marvell, their Sheeva core was developed from both the Intel XScale and > their own Feroceon CPU, both being ARMv5 ISA implementations. So one would assume > the Sheeva to be ARMv5 ISA compliant as well. But then there is this: > > "Compliant with the Cortex A8, Sheeva also supports both the ARMv6 and ARMv7 > instruction sets, making it the world's first dual ARM ISA compatible CPU." > http://www.marvell.com/technologies/cpu_history/cpu_history.jsp > > What's Sheeva then? ARMv5 (like XScale and Feroceon), ARMv6 or ARMv7 (like > Cortex-A8)? Or a combination of these? Very confusing. Can anyone shed some light, > please? > > > Edit: > > http://www.marvell.com/files/technologies/SheevaUntoldStory.pdf from August 2008 > provides some further clues: > > "2009 - A new flagship CPU: Newest CPU core features multi-Ghz performance, [...] > out-of-order execution, and full ARMv6 and ARMv7 compatibility" > (page 2, "Figure 1. Timeline of Marvell CPU development") > > "Marvell has extended its license to cover ARM v6 and v7, the most recent version of the > architecture. The company expects to sample its first ARM v7 CPU in late 2008." > (page 3) > > So it seems that contrary to the statement on the Marvell "History of CPU" webpage current > Sheeva core(s) are ARMv5 ISA compliant and *not* ARMv6 or ARMv7 ISA compliant but > *future* Sheeva cores are supposed to be.
To answer my own question from 9 months ago in conclusion:
There's currently 2 types of Sheeva cores: The older Sheeva PJ1, which implements ARMv5 ISA, and the new Sheeva PJ4, which implements ARMv7 ISA.
