> LibreSoC scalar instruction set (klick)

"Power ISA Scalar (SFFS) has not been significantly advanced in 12 years"

Power ISA v2.06 was released 14 years ago, v2.07 10 years ago. Everything happened 12 years ago apparently, always ;-)
(Besides, the current compliancy subsets including SFFS were first published as such with Power ISA v3.0C as recently as 3 years ago.)

Update:

> Several press releases from RED Semiconductor:
> "Vector+1 [...] SVP64 [...] Vantage"

Apparently, those terms have vanished from the prominent spots of the website. Instead, it's now about VISC. Maybe an advice by (one of) the new advisers?

Update:

> Statement on PowerPi by the Libre-SOC project lead and
> Technical Director of RED Semiconductor: […]
> https://lists.debian.org/debian-powerpc/2023/03/msg00014.html
> I'm not really sure what to make of this.

POWERπ got mentioned as ongoing project at EuroBSDCon 2023 by the Chair of the OpenPOWER Foundation's Technical Steering Committee:

https://www.youtube.com/watch?v=Tj4Q-m_WEh0 (4:25 and 32:03)

- open source (whatever that means)
- dual-core
- 500 EUR target price (up from 150 USD, see comment #213)

More interesting points from this presentation:
- Raptor will announce Power10-based hardware very soon (at 3:52 and 41:30)
- Microsoft will manufacture hardware based on Power ISA v3.1 / Power10 (Huh?)
- plan for workstations for 1000…1500 EUR target price (at 24:32 and 31:26)
- something called "PowerSBC" (which is apparently different from POWERπ)
- Single Board Computers (same as above?) in 2024/2025 (at 31:34)

(There're also many pure nonsense claims in this talk like the e6500-based PowerPC notebook project being Power ISA v3.1 (instead of v2.06), or IBM having been the only manufacturer of Power-based CPUs in the past, or POWER being from the 1960s, or going PPC64LE (2013/2014) and making the ISA royalty-free (2019/2020) happening at the same time, or new compliancy subsets starting with ISA v3.1 (instead of v3.0C), or OpenPOWER microcontroller systems currently being available.)

Very interesting, thanks for sharing @Andreas_Wolf!

What was not clear to me is the huge difference in processor instruction count needed to implement an ISA v3.1 CPU. Nice that you can get away with just about ~200 instructions. Feels more RISC-like also.

Also if it's true we will get ~1500 EUR Power10 boards early next year which would be earlier than the PowerPC notebook to be expected.

Quote:


yes, it will be nice, if...

A couple of years ago I have in plan to buy Talos II with Power 9, price these time with one 4-core CPU was around 2000 USD. But price start to rise very fast and today it is nearly 5000 USD. Even Blackbird with few PCIe is 3000 USD today. So I don't have any.

So if there will be Power 10 entry board with price around 1500 EUR, it is exactly for me. And MorpHOS or AmigaOS. But we will see if it will be fiction or real...

> What was not clear to me is the huge difference in processor
> instruction count needed to implement an ISA v3.1 CPU. Nice
> that you can get away with just about ~200 instructions.

As outlined in comment #186, implementing a Power ISA core with ~200 instructions (SFFS, which is LCS minus SIMD/64-bit/LE and some more) or even much less (SFS, which is SFFS minus FP) is also possible and has actually been done with Power ISA v2 (see the e200z0 core as extreme example), except that it was called 'category' back then instead of 'compliancy subset' it's called now.
IBM and the OpenPOWER Foundation proudly (see comment #165) and completely removed optionality in Power ISA v3.0 (2015) for application portability reasons, requiring compliant cores to implement the full instruction set, thus making any less-than-server CPUs virtually impossible to implement. Unsurprisingly, to date there has been no other Power ISA v3.0/3.0B implementation than IBM's own POWER9 (btw, despite what's claimed on Wikipedia, Microwatt/Chiselwatt lack VSX/VMX, so cannot be v3.0/3.0B-compliant). And with the release of v3.0C (2020), IBM and the OpenPOWER Foundation acted as if they added something new and never before seen to the Power ISA. In reality, with the introduction of the compliancy subsets they just corrected their severe mistake of deprecating ISA v2's quite successful category concept.
Overall, and as current developments like Libre-SOC are testimony of, it can only be good for the Power ecosystem that IBM and the OpenPOWER Foundation came to their senses and brought back the possibility to create smaller/embedded yet modern (i.e. ISA v3) Power cores without forcing to implement a ~1000 instructions behemoth, as well as allowed royalty-free use of the ISA as of v3.0C.

> if it's true we will get ~1500 EUR Power10 boards early next year

As I understand, that's meant to be complete systems, not just boards. But early next year? When was that said?

Quote:
Ah, my mistake. At 31:00 he starts talking about future hardware and shows a list, telling that it's ranked in order of arrival.

What will arrive early next year are the entry level rack servers. The Single Board Computers are hoped to be there by the end of next year. Workstations ought to arrive somewhere inbetween as the list is ranked but with no additional timeframe.

>> early next year? When was that said?

> At 31:00 he starts talking about future hardware and
> shows a list, telling that it's ranked in order of arrival.

That's another one of the many nonsenses in this talk, as at 31:44 he tells that the last two items of the list are already available. How can this be if the items are listed in arrival order? I suspect the items are actually listed in performance order from highest to lowest, and he just muddled it up.
Of course, this doesn't rule out the possibility of the workstations indeed arriving between the server racks and the SBCs ;-)

Quote:


With that price I would chose another name, without the "pi". More than a decade ago when I pursued such a plan for a while (a 5125 based mini board) I had doubts about the target price of 50 US$ -80 US$. 500US$ is just way off for the general audience.

Update:

> Raptor will announce Power10-based hardware very soon

Seems the Power10 claim was not correct either as it's now actually announced to be another CPU called S1 by a chip design company called Solid Silicon:

"Raptor Computing Systems announced it has partnered with US-based Solid Silicon Corporation as its future CPU provider for continued secure, fully open systems and servers [...]. Raptor Computing Systems will be using Solid Silicon S1 CPUs with embedded POWER ISA 3.1-compliant, server class cores as the fully owner-controlled, blob-free successor to its IBM POWER9-powered solutions, with expected availability of systems by late 2024."
https://www.businesswire.com/news/home/20231019873615/en/

Some more statements from Raptor:

"Details will be made public early 2024 [...]. What we can say right now is to expect competitive core performance and overall connectivity, including PCIe Gen 5! Smaller offerings are also in the works for 2025."
https://twitter.com/RaptorCompSys/status/1715173990556414412

"POWER ISA 3.1-compliant server class device [...] will be integrated into upcoming "Talos III" / "Blackbird II" systems, among other potential offerings."
https://twitter.com/RaptorCompSys/status/1715233204037460174

"S1 [...] has DDR5 capability."
https://twitter.com/RaptorCompSys/status/1715412620856156377

"we are focusing more on successors to the Talos / Blackbird with the S1."
https://twitter.com/RaptorCompSys/status/1715425175532167652

"The S1 sits in a physical and power footprint closer to Sforza than LaGrange."
https://twitter.com/RaptorCompSys/status/1715426316617740553


Edit: added more statements

[ Edited by Andreas_Wolf 20.10.2023 - 20:39 ]

Thanks for your well researched update Andreas!

Your 1st link states among other things Solid Silicon Corporation is a fabless silicon company [...]. So I wonder who is going to produce this S1 CPU and which node size and technology will be used?

Supposedly it will be better than the 14 nm (FinFET) of the POWER 9, but to what extent? While I think the POWER 9 performance still is pretty decent it's idle power consumption is not so much. Not that we would care much as G5 MorphOS users.

> who is going to produce this S1 CPU and which node size
> and technology will be used?

No definite answers on this yet but some more general info:

"I asked Timothy Pearson at Raptor about the S1's specs, and he said it's a PCIe 5.0 DDR5 part running from the high 3GHz to low 4GHz clock range, with the exact frequency range to be determined. (OMI-based RAM not required!) The S1 is bi-endian, SMT-4 and will support at least two sockets with an 18-core option confirmed for certain and others to be evaluated."
https://www.talospace.com/2023/10/the-next-raptor-openpower-systems-are.html

Update:

> Seems the CP1 has been renamed the HX-C1000.

Like that one is essentially a Chinese POWER8, I guess the new HX-C2000 is essentially a Chinese POWER9.*

https://www.tomshardware.com/news/china-chip-ibm-open-source-power-isa-x86-arm-server-cpu-us-sanctions


Edit: Wrong assumption, see correction in comment #243.

[ Edited by Andreas_Wolf 08.12.2023 - 12:42 ]

Interesting turn of events! All of a sudden POWER based chips are popping out all over the place. Or more like - are going to pop out next year.

>>> Seems the CP1 has been renamed the HX-C1000.

>> Like that one is essentially a Chinese POWER8, I guess
>> the new HX-C2000 is essentially a Chinese POWER9.

> Interesting turn of events! All of a sudden POWER based chips are popping
> out all over the place. ;-) Or more like - are going to pop out next year.

That's a little exaggerated, I'd say ;-)
Btw, I have to correct my assumption that HX-C2000 is POWER9. It's still essentially POWER8 like the HX-C1000, but with PCIe upgraded from v3 to v5, memory upgraded from DDR4 (via Centaur) to DDR5 (directly connected) and other upgrades/changes to the core and "uncore":

https://lists.ozlabs.org/pipermail/linuxppc-dev/2023-November/265870.html

So in essence, it's a modified/improved POWER8 (but still no POWER9 or higher) combined with Power10-level on-chip controllers.

Update:

> Libre-SOC project lead and Technical Director of RED Semiconductor

There seems to be some severe falling-out between him and RED Semiconductor, rendering him being no longer involved with the company:

"RED Semiconductor Ltd's Directors have [...] removed me from the Board of Directors despite being a majority shareholder, have withdrawn resources that severely compromise Libre-SOC's ability to fulfil its EU Grant funded work, and as a result violated the Libre-SOC Charter which *as a company* they have not agreed to because it was only through me in my dual capacity as Founder and former Director of RED, combined with Founder and Team Lead of Libre-SOC, that they had two-way access to Libre-SOC resources. with James Lewis (CEO) instructing employees to focus exclusively on RED Semiconductor interests, to the detriment of Libre-SOC research and grant funded work, it is abundantly clear that RED Semiconductor Ltd intends to use FOSDEM as a means and method of recruiting people who would otherwise be interested in working on FOSS and on Libre-SOC work, where for the past 5 years we have had extreme difficulty finding anyone, because the level of technical difficulty is so high that anyone with the right skillset can earn 5 to 8 times more money than is available from NLnet EU Grant funding."
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-January/006005.html

"RED Semiconductor Ltd Directors, CALDERWOOD and LEWIS, […] have made a false declaration to Companies House that i "resigned" on 16th January 2023 from the company that i founded. […] they have hijacked NGI Search EU grant funding, destroyed morale in my team, we have lost two team members, i have had to put on hold inviting potential team members i was planning to contact […]. […] NLnet's Director Bob Goudriaan informed us that the European Commission […] was so alarmed by CALDERWOOD and LEWIS's efforts to seize control of EU grants that they told NLnet that our two NLnet Grant applications totalling EUR 185,000 are summarily terminated, and that all future EU grant applications by Libre-SOC will be immediately rejected. i was also unable to travel to FOSDEM24 to give presentations, as they also attempted to hijack our Devroom, inserting sub-standard talks with zero consultation or discussion at the last minute. i was able, barely, to get the sub-standard talks removed, […] but the permanent damage caused to my project, and the team's morale, as well as my standing with FOSDEM, is incalculable. they have also completely ignored NLnet's Mediator (Brian), whom i was allocated by NLnet to help get them under control, after such severe violations of our Charter […]."
https://lists.libre-soc.org/pipermail/libre-soc-isa/2024-March/002908.html

"Luke […] has to understand there is a limit and to protect ourselves we will have to take legal action […]. […] we were legally required remove Luke from our company for breaches of the Companies and Employment Acts due to his dangerous and threatening behaviour towards other staff […]. […] We have legally defended our position when he tried to steal a grant application made in our name, which NLnet confirmed by suspending Luke's/LibreSOC's ability to raise new grants, however we are entitled to protect ourselves from theft. […] Luke […] had over six months of formal warnings from three different directors of the company about his behaviour, and was dismissed lawfully when he failed to change his behaviour. Even then we offered him a full Technical Consultancy, equivalent remuneration and retaining his shares, but outside the company rather than as an employee, which he refused."
https://lists.libre-soc.org/pipermail/libre-soc-isa/2024-March/002910.html

"we met and discussed at some length with Brian (the mediator) at FOSDEM, with Mirko, Bob and Michiel over the two days. Brian had already concluded, given Lukes postings […], there was no possibility of mediation given Lukes state of mind, and Luke subsequently falsely stating publicly that Michiel had acted in an unethical manner has I suspect only reinforced that view. Mediation is all about re-engaging, and we do not wish to re-engage and even if we were inclined to do so we legally cannot. Other members of RED would take legal action against us for failing to protect them from Luke’s assaults and abuse. Luke is under the impression that our actions were malicious, that we are at fault and we should reverse everything we have done. Quite the opposite, removing Luke has severely hampered us and required us to clean room our development work, which is now travelling a completely different path. Having said that we are now beyond where we would have been with Luke as part of the team. I am happy to share this with you at a future date. Brian agreed that you cannot mediate a lawful act under criminal statute and that we had acted properly, given Lukes behaviour and the evidence he could see of it continuing. Regardless Luke stopping posting slanderous and defamatory post requires no mediation to achieve unless it is done by a judge in a court of law […]. We are already disengaged and, beyond where we have to take legal action to defend ourselves, we have already stated we want nothing more to do with Luke. […] Luke is lying on just about everything to avoid facing up to the reality of the situation he has brought upon himself. Luke by his behaviour is continuing to force our hand and just as we acted to remove him from the company, we will take the next legal steps to protect ourselves."
https://matrix.org/_matrix/media/v3/download/matrix.org/FBbCzvGiwmfhsqsslBlAteQm
https://libre-soc.org/irclog/%23libre-soc.2024-03-16.log.html#t2024-03-16T08:35:41

"when discussing the vast amount of funds i was expected to pour into the company to pay myself and **TWO** employees salaries (GBP 8,000) after i had specifically warned the Directors well over six months prior that i was unable to do work due to RAYMOND's abuse, and that there would be a "black hole" in the finances that they needed to help cover by finding Grant or other money, CALDERWOOD intimidated me into putting NLnet Grant RFPs in RED Semiconductor's name instead of mine [...]. [...] i had no idea that CALDERWOOD could turn so dangerous. if i had known i would never have invited him to be the Chairman of RED Semiconductor Ltd. it is he himself who explained to me that it is the Chairman who holds all the power in a Company. [...] i suspect that CALDERWOOD and LEWIS are being advised that they can seize control of our work without seeking either Trademark or Patent Licenses, or worse that as "compensation" for what they believe is Libel [...] they can seize control of all of the NLnet Grant funded work of the past six years. that would be absolutely catastrophic for us because it is in direct violation of NLnet's "Works for the Public Good" mandate to have Corporations control 100% of the Copyright, Trademarks and Patents [...]."
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-March/006138.html

"All went well until […] he was becoming dangerously abusive to other staff members combined with other problems he was removed for violations of the The Companies Act and Employment Legislation. In short we had a duty of care to the other employees […] behaviour. He has not taken this well and has been openly slanderous and libellous about his former colleagues. […] Acting was very hard but we could not avoid dealing with his behaviour which was becoming physically abusive to other members of staff. He was sacked. […] he was removed for gross misconduct and abusing his legal position as a director."
https://libre-soc.org/irclog/%23libre-soc.2024-03-18.log.html#t2024-03-18T08:12:42

"a release date of the Simple-V specification is delayed indefinitely pending resolution of the harrassment, Coercive Controlling Behaviour and stalking by CALDERWOOD and LEWIS as Directors of my hijacked company, RED Semiconductor Ltd. this means that whilst Trademark Licenses may be sought, any commercial licensees need to be aware that the date when they may put out commercial silicon is now unknown, pending resolution of the damage done to myself and the team, by CALDERWOOD and LEWIS. CALDERWOOD and LEWIS have been notifed multiple times of the route by which resolution is to be achieved, should they choose to do so. i have received *no word* from NLnet's mediator, Brian. additionally Denton's were informed that CALDERWOOD and LEWIS are not automatically granted Trademark or Patent Rights, and that they have sought neither in any communication of any kind."
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-March/006143.html


Edit: added some more messages

[ Edited by Andreas_Wolf 13.04.2024 - 16:08 ]

Oh my... just the kind of news one would expect and is accustomed to in the Amiga scene.

> Oh my... just the kind of news one would expect and is
> accustomed to in the Amiga scene. :-D

It doesn't get better:

https://www.phoronix.com/news/Libre-SoC-NLNet-Funding-Lost

Update:

> the project first switched ISA from RISC-V to Power

Back to the roots it seems:

"the current plan is that we'll likely switch back to risc-v. […] issues with IBM apparently effectively blocking our proposed additions to PowerISA... […] iirc VCs being more willing to fund RISC-V designs is also an aspect […] it turns out that IBM blocking is not exactly correct, but by that point we already decided... […] though they still are going extremely slowly on some parts (which aren't public afaik)"
https://libre-soc.org/irclog/%23libre-soc.2024-03-28.log.html#t2024-03-28T19:54:22

"VISC [...] extends the capabilities of RISC-V [...]. VISC is an accelerated RISC-V microprocessor core [...]. [...] The VISC execution architecture is created as a fully functional stand-alone RISC-V compatible core [...]. [...] RED Semiconductor’s mission is to develop and deliver a new class of algorithmic microprocessor IP optimised for RISC-V [...]."
https://redsemiconductor.com/visc-licensable-high-performance-processor-architecture-risc-v/

"it is a direct copy. […] i taught CALDERWOOD about Simple-V (TM) and how to implement it and apply it to other ISAs. remember we have done *both* RV *and* OpenPOWER, and in private conversations i discussed how i could apply SV to other ISAs. i also told them where to find the original Simple-V RISC-V-based work (sv-spike). LEWIS then came up with the word "VISC" and recently added "TM" after it. the text on that page clearly states "we can apply VISC to other ISAs". in other words they are stealing the Vectorisation technique, known as Simple-V, claiming it is theirs under the term "VISC" and claiming it is Trademarked. […] it's actually *identical* […]."
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-April/006187.html

Apparently, the decision to refocus on RISC-V was already arrived at in November 2023, so months before the falling-out:
https://libre-soc.org/nlnet_2023_simplev_riscv/
https://libre-soc.org/nlnet_2023_simplev_riscv_binutils/
https://libre-soc.org/meetings/sync_up/sync_up_2023-11-22/
https://libre-soc.org/meetings/southampton/southampton_2023.nov.22/
https://libre-soc.org/meetings/dmitry_2023-11-24/
https://libre-soc.org/meetings/sync_up/sync_up_2023-11-28/

Further interesting quotes regarding the falling-out:

"they have LITERALLY lifted my entire work, […] the entire concept behind Simple-V […], there is absolutely no doubt whatsoever that this is blatant theft."
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-April/006199.html

"CALDERWOOD and LEWIS […] wrote to the UK Minister for Science Technology and Innovation claiming that they had acted lawfully by taking legal advice on how to seize control of RED Semiconductor Ltd. […] they think they know better, they think they understand (and own) Simple-V, therefore they can make it a success, fact is they don't own it and don't have the skill or knowledge. with them at the helm it is *guaranteed* that they will fuck up or abortionalise Simple-V, jeapordising its chances and destroying its reputation. oh and because they attempted to seize control of NLnet grants despite them flat out *not qualifying* for NLnet grants over EUR 50,000, we cannot continue with future valuable SV research."
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-April/006207.html


Edit: added some more links

[ Edited by Andreas_Wolf 28.04.2024 - 10:52 ]

Update:

> POWER10 has emerged on the roadmap

First public information on Power11 are there. Power11 must be the very first IBM POWER/Power generation with no ISA or microarchitectural improvements in the CPU core over the previous generation.

"CPU, MMU and user (ELF_HWCAP) features are unchanged vs P10."
https://lists.ozlabs.org/pipermail/linuxppc-dev/2024-February/268490.html

"Power11 core is same as Power10"
https://lists.gnu.org/archive/html/qemu-ppc/2024-04/msg00328.html