Update:

>> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/
>> "PowerPi" sounds interesting. Alas, no details yet.

> Some small details: [...]

Some more details on PowerPi / POWER Pi / POWERπ from OpenPOWER Summit NA 2021:

- SBC with dual-core or quad-core SoC ASIC
- slightly bigger than Raspberry Pi
- 150 USD max

https://www.youtube.com/watch?v=RCSKQoO5AEs (5:59-6:43)
https://www.youtube.com/watch?v=58ZmyKuB-04 (15:49-17:50)

Nice! Thanks for your constant updates on this topic @Andreas_Wolf!

Update:

> Power ISA 3.1 (POWER10) spec

Power ISA 3.1B spec released as of September 2021. Seems that this is what Power10 actually implements.

https://files.openpower.foundation/s/dAYSdGzTfW4j2r2/download/OPF_PowerISA_v3.1B.pdf
https://wiki.raptorcs.com/w/images/d/d3/OPF_PowerISA_v3.1B.pdf
https://openpowerfoundation.org/specifications/isa/


Edit: added another URL

[ Edited by Andreas_Wolf 23.02.2023 - 19:01 ]

Update:

> Looks like the RED Semiconductor company has been established
> for the purpose of commercializing the Libre-SOC technology:
> https://www.redsemiconductor.com

"The processor [...] will be able to run x86 code in native mode thanks to emulation capabilities, according to David Calderwood, chairman of the company. [...] The x86 emulation capability may be the result of technology that came to IBM when it acquired Transitive Corp. in 2008."
https://www.eenewsanalog.com/en/uk-startup-is-raising-funds-for-open-power-processor/

Wait, "native mode" or "emulation", which one is it? If the former, I'm not sure the actual developers of the CPU are aware of this capability announced by the company chairman. The article author's reference to long-abandoned, 32-bit-only QuickTransit/PowerVM Lx86, which is probably pulled out of thin air, implies a purely software-based emulation, in which case I'm not sure what this would have to do with the actual CPU design. Furthermore, I doubt that IBM would grant free use of this technology.


Edit: RED Semiconductor is now OpenPOWER Foundation member.
Edit2: https://redsemiconductor.com/red-semiconductor-joined-the-openpower-foundation/

[ Edited by Andreas_Wolf 02.10.2022 - 02:01 ]

binutils got LibreSOC support recently (klick). And it looks like it got Altivec + VSX support too (klick).

> it looks like it got Altivec + VSX support

There's no way on earth that Libre-SOC implements VSX or VMX/AltiVec, or ever will (see also comment #202). The Libre-SOC development lead absolutely despises the SIMD concept, as opposed to true vector processing.

"Libre-SOC will be compliant with the Scalar Floating-Point Subset (SFFS) i.e. is not implementing VMX/VSX […]. Prior to the formation of the Compliancy Levels first introduced in v3.0C and v3.1 the progressive historic development of the Scalar parts of the Power ISA assumed that VSX would always be there to complement it. However With VMX/VSX not available in the newly-introduced SFFS Compliancy Level, the existing non-VSX conversion/data-movement instructions require a Vector of load/store instructions (slow and expensive) to transfer data between the FPRs and the GPRs. For a modern 3D GPU this kills any possibility of a competitive edge. Also, because SimpleV needs efficient scalar instructions in order to generate efficient vector instructions, adding new instructions for data-transfer/conversion between FPRs and GPRs multiplies the savings. […] (The existing Scalar instructions being FP-FP only is based on an assumption that VSX will be implemented, and VSX is not part of the SFFS Compliancy Level. An earlier version of the Power ISA used to have similar FPR<->GPR instructions to these: they were deprecated due to this incorrect assumption that VSX would always be present)."
https://libre-soc.org/openpower/sv/int_fp_mv/

"Scalar bitmanipulation is justifiable for the exact same reasons the extensions are justifiable for other ISAs. The additional justification for their inclusion where some instructions are already (sort-of) present in VSX is that VSX is not mandatory, and the complexity of implementation of VSX is too high a price to pay at the Embedded SFFS Compliancy Level."
https://libre-soc.org/openpower/sv/vector_isa_comparison/

"Vectorisation of the VSX Packed SIMD system makes no sense whatsoever, the sole exceptions potentially being any operations with 128-bit operands […]. SV effectively replaces the majority of VSX, requiring far less instructions, and provides, at the very minimum, predication (which VSX was designed without)."
https://libre-soc.org/openpower/sv/svp64/appendix/

"When combined with SV, scalar variants of bitmanip operations found in VSX are added so that the Packed SIMD aspects of VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios."
https://libre-soc.org/openpower/sv/bitmanip/

"Whilst SVP64 is only 5 instructions the heavy focus on VSX for the past 12 years has left the SFFS Level anaemic and out-of-date compared to ARM and x86. This is very much a blessing, as the Scalar ISA has remained clean, making it highly suited to RISC-paradigm Scalable Vector Prefixing. Approximately 100 additional (optional) Scalar Instructions are up for proposal to bring SFFS up-to-date. None of them require or depend on PackedSIMD VSX (or VMX)."
https://libre-soc.org/openpower/sv/

Quote:
Sounds reasonable. But if you are correct the binutils definition for LibreSOC
"libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64)
must stand for something else?

> if you are correct the binutils definition for LibreSOC
> "libresoc", ([...] PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX [...])
> must stand for something else?

According to the project lead on IRC, the current binutils definition for "libresoc" is simply wrong:

"i suspect those flags will have to be reduced to:
PPC_OPCODE_ISEL (if that is for the isel instruction)
PPC_OPCODE_POWER9
PPC_OPCODE_SVP64
and that's probably it"
https://libre-soc.org/irclog/%23libre-soc.2022-08-12.log.html#t2022-08-12T04:50:46

> dubious statements from the project lead [...]

Seems he now passes as a "Dr." and IBM employee ;-)

Update:

> Some more details on PowerPi / POWER Pi / POWERπ [...]

As reported by MorphZone member Peter "czp" Czanik from EuroBSDCon 2022:

"Toshaan Bharvani, who participates in the work of the OpenPower Foundation, [...] talked a few words about the upcoming Power SBC arriving hopefully mid-next year."
https://peter.czanik.hu/posts/eurobsdcon2022/

Thanks for your constant updates on this matter!

However not much news apart from your cited statement. A bit of secrecy for this OpenPower hardware..

> Thanks for your constant updates on this matter!

You're welcome.

> However not much news apart from your cited statement.

As soon as the recording of the talk is online, I'll report here in case it had more newsworthy information on the PowerPi / POWER Pi / POWERπ project.

> A bit of secrecy for this OpenPower hardware.. ;-)

Yes, unfortunately, the PowerPi SIG operates in complete confidentiality.

Update:

> Looks like the RED Semiconductor company has been established
> for the purpose of commercializing the Libre-SOC technology:
> https://www.redsemiconductor.com

Several press releases from RED Semiconductor:

"Augmenting the OpenPOWER ISA first developed by IBM, RED Semiconductor is using the draft SVP64 implementation of Vector+1 to design a family of new microprocessors to be marketed as their Vantage family, of which the first device a 2-core will be the Vantage-Luna."
https://redsemiconductor.com/libre-soc-red-semiconductor-announce-partnership/ (January 3, 2022)

"Extending the POWER ISA first developed by IBM, RED Semiconductor is using the Libre-SOC Draft SVP64 implementation of Vector+1 to design its ‘Vantage’ family of new microprocessors which will be marketed globally for high performance computing applications. "
https://redsemiconductor.com/red-semiconductor-joined-the-openpower-foundation/ (September 30, 2022)

"RED Semiconductor is working with industry partners to accelerate the implementation of a 1-core ‘Vantage’ cipher-accelerator microprocessor chipset [...]. Planned for first-customer shipments in early 2024, the ‘Vantage1’ chip will be targeted at data security and privacy applications [...]."
https://redsemiconductor.com/wp-content/uploads/2022/11/red-semiconductor-chacha20-cipher-performance-1.pdf (page 4; November 10, 2022)

And from the homepage:
"Supporting native Power ISA and translated x86 and ARM instructions, SVP64 will enable developers to break free from the constraints of traditional processing platforms, with a rapid conversion to SVP64 hardware and code architecture. [...] Advanced microprocessor chip-set optimized for OS-based compute-intensive applications: - Initial 2 and 8 core variants will scale to 1k+ cores"

[ Edited by Andreas_Wolf 15.11.2022 - 10:31 ]

Update:

>> A bit of secrecy for this OpenPower hardware.. ;-)

> Yes, unfortunately, the PowerPi SIG operates in complete confidentiality.

Statement on PowerPi by the Libre-SOC project lead and Technical Director of RED Semiconductor:

"Toshaan Bharvani started the PowerPI initiative, but it was soon taken over by naive people believing that you can get a 5 watt system to do 4-core 3 ghz 7 nm with 128-bit-wide DDR3/4/5 memory and multiple lanes of PCIe and multiple lanes of OpenCAPI in under a budget of USD 10 million, when 7nm Mask Charges are $10 million on their own."
https://lists.debian.org/debian-powerpc/2023/03/msg00014.html

I'm not really sure what to make of this.

> of course, also this significant event doesn't come without
> some dubious statements from the project lead:
> "Libre-SOC […] is the first wholly-independent Power ISA ASIC
> outside of IBM to go Silicon in 12 years." […]
> He tried again and failed once more:
> "our […] test ASIC […] is […] the world's first Power ISA 3.0 [ASIC]
> outside of IBM to reach Silicon in over 12 years."

Seems that whenever he has not the slightest clue when it was that something happened or became available, he claims it was (over) 12 years ago:

"what has been developed […] is the biggest upgrade to the Power ISA since Motorola's VLE Book of over 12 years ago"
https://lists.debian.org/debian-powerpc/2023/04/msg00008.html

Book VLE was officially added to the Power ISA with v2.03 in 2006, so 17 years ago (and then completely deleted from it with ISA v3.0 in 2015). The VLE instruction set itself (as well as processors implementing it) was even available from several years earlier than that, as extension to Book E.

An RFC with the full list of the LibreSoC scalar instruction set (klick), waiting for comments before external review of the OpenPower ISA working group.

> LibreSoC scalar instruction set (klick)

"Power ISA Scalar (SFFS) has not been significantly advanced in 12 years"

Power ISA v2.06 was released 14 years ago, v2.07 10 years ago. Everything happened 12 years ago apparently, always ;-)
(Besides, the current compliancy subsets including SFFS were first published as such with Power ISA v3.0C as recently as 3 years ago.)

Update:

> Several press releases from RED Semiconductor:
> "Vector+1 [...] SVP64 [...] Vantage"

Apparently, those terms have vanished from the prominent spots of the website. Instead, it's now about VISC. Maybe an advice by (one of) the new advisers?

Update:

> Statement on PowerPi by the Libre-SOC project lead and
> Technical Director of RED Semiconductor: […]
> https://lists.debian.org/debian-powerpc/2023/03/msg00014.html
> I'm not really sure what to make of this.

POWERπ got mentioned as ongoing project at EuroBSDCon 2023 by the Chair of the OpenPOWER Foundation's Technical Steering Committee:

https://www.youtube.com/watch?v=Tj4Q-m_WEh0 (4:25 and 32:03)

- open source (whatever that means)
- dual-core
- 500 EUR target price (up from 150 USD, see comment #213)

More interesting points from this presentation:
- Raptor will announce Power10-based hardware very soon (at 3:52 and 41:30)
- Microsoft will manufacture hardware based on Power ISA v3.1 / Power10 (Huh?)
- plan for workstations for 1000…1500 EUR target price (at 24:32 and 31:26)
- something called "PowerSBC" (which is apparently different from POWERπ)
- Single Board Computers (same as above?) in 2024/2025 (at 31:34)

(There're also many pure nonsense claims in this talk like the e6500-based PowerPC notebook project being Power ISA v3.1 (instead of v2.06), or IBM having been the only manufacturer of Power-based CPUs in the past, or POWER being from the 1960s, or going PPC64LE (2013/2014) and making the ISA royalty-free (2019/2020) happening at the same time, or new compliancy subsets starting with ISA v3.1 (instead of v3.0C), or OpenPOWER microcontroller systems currently being available.)

Very interesting, thanks for sharing @Andreas_Wolf!

What was not clear to me is the huge difference in processor instruction count needed to implement an ISA v3.1 CPU. Nice that you can get away with just about ~200 instructions. Feels more RISC-like also.

Also if it's true we will get ~1500 EUR Power10 boards early next year which would be earlier than the PowerPC notebook to be expected.

Quote:


yes, it will be nice, if...

A couple of years ago I have in plan to buy Talos II with Power 9, price these time with one 4-core CPU was around 2000 USD. But price start to rise very fast and today it is nearly 5000 USD. Even Blackbird with few PCIe is 3000 USD today. So I don't have any.

So if there will be Power 10 entry board with price around 1500 EUR, it is exactly for me. And MorpHOS or AmigaOS. But we will see if it will be fiction or real...

> What was not clear to me is the huge difference in processor
> instruction count needed to implement an ISA v3.1 CPU. Nice
> that you can get away with just about ~200 instructions.

As outlined in comment #186, implementing a Power ISA core with ~200 instructions (SFFS, which is LCS minus SIMD/64-bit/LE and some more) or even much less (SFS, which is SFFS minus FP) is also possible and has actually been done with Power ISA v2 (see the e200z0 core as extreme example), except that it was called 'category' back then instead of 'compliancy subset' it's called now.
IBM and the OpenPOWER Foundation proudly (see comment #165) and completely removed optionality in Power ISA v3.0 (2015) for application portability reasons, requiring compliant cores to implement the full instruction set, thus making any less-than-server CPUs virtually impossible to implement. Unsurprisingly, to date there has been no other Power ISA v3.0/3.0B implementation than IBM's own POWER9 (btw, despite what's claimed on Wikipedia, Microwatt/Chiselwatt lack VSX/VMX, so cannot be v3.0/3.0B-compliant). And with the release of v3.0C (2020), IBM and the OpenPOWER Foundation acted as if they added something new and never before seen to the Power ISA. In reality, with the introduction of the compliancy subsets they just corrected their severe mistake of deprecating ISA v2's quite successful category concept.
Overall, and as current developments like Libre-SOC are testimony of, it can only be good for the Power ecosystem that IBM and the OpenPOWER Foundation came to their senses and brought back the possibility to create smaller/embedded yet modern (i. e. ISA v3) Power cores without forcing to implement a ~1000 instructions behemoth, as well as allowed royalty-free use of the ISA as of v3.0C.

> if it's true we will get ~1500 EUR Power10 boards early next year

As I understand, that's meant to be complete systems, not just boards. But early next year? When was that said?

Quote:
Ah, my mistake. At 31:00 he starts talking about future hardware and shows a list, telling that it's ranked in order of arrival.

What will arrive early next year are the entry level rack servers. The Single Board Computers are hoped to be there by the end of next year. Workstations ought to arrive somewhere inbetween as the list is ranked but with no additional timeframe.

>> early next year? When was that said?

> At 31:00 he starts talking about future hardware and
> shows a list, telling that it's ranked in order of arrival.

That's another one of the many nonsenses in this talk, as at 31:44 he tells that the last two items of the list are already available. How can this be if the items are listed in arrival order? I suspect the items are actually listed in performance order from highest to lowest, and he just muddled it up.
Of course, this doesn't rule out the possibility of the workstations indeed arriving between the server racks and the SBCs ;-)

Quote:


With that price I would chose another name, without the "pi". More than a decade ago when I pursued such a plan for a while (a 5125 based mini board) I had doubts about the target price of 50 US$ -80 US$. 500US$ is just way off for the general audience.