Yes not bad specs, if they can get the price reasonable and the CPU MHz up a bit, like they did with the original SAM, it may be a nice little box.

MorphOS Port anyone? :)

Addendum:

> compared to the e500mc the e5500 has twice the single precision
> performance per clock and up to quadruple the double precision
> performance per clock.

Nothing about FPU performance, but an interesting comparison between e500mc and e5500 regarding integer related performance:

http://www.power.org/events/POWERWEBINAR082010/PowerOrgWebinarMilAeroGieske-1.pdf (page 13)

According to the rightmost chart the e5500 delivers only about 76% of the DMIPS per Watt delivered by the e500mc.

Performance per watt figures don't scare me as much as that next comment "e500mc & e5500 have less single-thread performance than some cores".

> Performance per watt figures don't scare me
> as much as that next comment

Really? That comment is in no way surprising to me. The "e5500" bar in the leftmost chart shows the e5500 at 2.2 GHz, i.e. 6600 DMIPS. The "MaxPerf" bar to the right is twice as high as the "e5500" bar, i.e. 13200 DMIPS. While I don't know which is the best performing core in the whole wide world in terms of DMIPS, I'm sure that 13200 DMIPS is no unmatched figure.
For lists of figures for various processors refer to:

http://www.roylongbottom.org.uk/dhrystone%20results.htm
("Dhry2", Opt" column is the one to look at)

http://www.anime.net/~goemon/benchmarks.html
(values in the "RESULT" column must be divided by 1757 to get DMIPS figures)

Yes, I guess if the statement could be so obtuse (not even mentioning what "cores" they're talking about) that it doesn't carry much weight.
But does the DMIPS per watt figure make any real statement about the relative power of each processor, or is it just a measure of efficiency?

> does the DMIPS per watt figure make any real statement
> about the relative power of each processor, or is it just
> a measure of efficiency?

Just imagine the inverse, i.e. Watts per DMIPS (where lower is better of course), which means how much Watts are needed to compute 1 DMIPS. This way it is more easy to understand what this measure of efficiency (there you go) in the shape of a combination of DMIPS and Watts means.
The relative DMIPS performance of the cores, on the other hand, is shown by the leftmost chart, as I explained already.

In case that with "power" you mean rather electrical power, not performance:

(1) 2.2 GHz e5500 has 1.76 times the DMIPS performance of 1.5 GHz e500mc.
(2) 2.2 GHz e5500 needs 1.32 times the Watts to compute 1 DMIPS compared to 1.5 GHz e500mc.

Results:
A) 2.2 GHz e5500 draws 1.76 * 1.32 = 2.3 times the power of the 1.5 GHz e500mc.
B) At the same clock, while being only 20% more performant, the e5500 draws 58% more power than the e500mc.

No Andreas, you had it right the first time, although the second set of figures is also interesting.
What would you think creates these inefficiency issues? The e5500 is clearly a superior processor when compared to the e500, but from both of those points of view it the e5500 suffers in this comparison.

> What would you think creates these inefficiency issues?

Good question. But I've to admit that I really don't know. Freescale presented the e5500 as being basically a 64 bit capable version of the e500mc (hence the 'e500mc64' moniker) with an enhanced FPU (but which of course is irrelevant in terms of integer performance). With that said it's really strange that in terms of DMIPS the e5500 is 24% less efficient than the e500mc.

> for all we know, someone could very well have been working on a non-PPC version
> of MorphOS for a long time already...

If that's the case then it's probably not an x86 version at least. From Commodore USA's CTO:

"When I contacted Team MorphOS, Ralph S told me they had no intention of porting to x86 any time soon."
http://www.amiga.org/forums/showpost.php?p=579267

Addendum:

>> how willing pointing point operations compare between
>> the 5500 and the Titan?

> All processors from Applied Micro which have an FPU [...] deliver 2.0 MFLOPS per MHz in
> both single and double precision. [...] compared to the e500mc the e5500 has twice the
> single precision performance per clock and up to quadruple the double precision
> performance per clock. [...] Freescale's e500mc presentation notes that e500mc has
> "same floating point unit as e300", but which is half clocked in relation to the core clock
> and thus half performant. So I'd conclude that compared to the e300 the e5500 has the
> same single precision performance per clock and up to twice the double precision
> performance per clock. Now we only need the floating point performance figures for the
> e300 to get the whole picture ;-)

I found that 603e/G2_LE/"e300c0" does only 0.4 MFLOPS per MHz according to a posting on powerdeveloper.org:

http://www.powerdeveloper.org/forums/viewtopic.php?p=13781#13781

I don't know if that's single or double precision (or even both) but either way if both my interpretation of that figure and my assumptions above are correct, then it doesn't bode too well for the floating point performance of the e5500 in general as well as compared to the Titan (or probably rather its replacement) specifically.

Update:

>> Seems we know at least the name of the Titan
>> replacement core based processor: APM86xxx.

> "Applied Micro will announce a new family of multicore SoC processors that use
> SMP and AMP architectures to address the demanding needs of applications
> within the Enterprise, Data Center, Industrial, Gateways / Access Point, and more."
> http://www.appliedmicro.com/events/linley2010.php
> http://www.linleygroup.com/Seminars/conference_fall_program_day1.html
> http://www.linleygroup.com/Seminars/conference_fall_talks.html

Seems like the APM86xxx's Power Architecture core(s) may be complemented by a nice co-processor core:

http://www.tensilica.com/news/335/330/AppliedMicro-Picks-Tensilica-s-Dataplane-Processors-for-High-Throughput-Communications-Chip-Design.htm
http://www.tensilica.com/products/xtensa-customizable/xtensa-lx.htm

Edit:

I found an interesting PDF presentation file dating August 2010 over there.
The most interesting pages are #16, which shows a product roadmap mentioning "Future Viper SoCs", and #18, which reads "Viper Technology -> Breakthrough Performance at Disruptive Cost Basis".
To my surprise, the roadmap on page 16 still contains the Titan core based "Gemini" (APM83290), which had been semi-officially declared dead one month before. Strange.

Further insightful (but older) documents are this one (August 2009) and that one (October/November 2009). Both documents's pages 11 show a product roadmap including not only Titan (still vivid at that time) but also dummy-named products "PPC-A" ("Avail 1H 2010"), "PPC-B" ("Avail 2H 2010") and "PPC-C" ("Avail 1H 2012").

[ Edited by Andreas_Wolf on 2010/9/24 23:49 ]

Addendum:

> To my surprise, the roadmap on page 16 still contains the Titan core based "Gemini"
> (APM83290), which had been semi-officially declared dead one month before. Strange.

It gets even better. I really don't know what to make out of this:

------------------------------
Allan Mishan - Brigantine Advisors
Okay and then on the Titan products, when you expect to ship production revenue? I know that that was originally supposed to be happening sometime in the second half of this calendar year. I don't know if you can get more specific on that.

Bob Gargus - Applied Micro Circuits Corporation - CFO
So we had said all along that we didn't think it would start shipping for revenue until the December quarter. I think it's still the December/March quarter roughly before we start to see revenue from that.

Paramesh Gopi - Applied Micro Circuits Corporation - President and CEO
Yep.
------------------------------
http://www.sec.gov/Archives/edgar/data/711065/000119312510177397/dex992.htm (transcript of Applied Micro's first quarter 2011 earnings conference call in late July 2010, i.e. several weeks *after* abandonment of Titan was reported)

It doesn't make any sense to me. Are these answers from the conference call together with the most recent product roadmap presentation just a part of a farce to keep their investors and shareholders happy and the analysts favourable by deluding them? Or is Titan really still alive?

I found it strange that they moved away from it in the first place. Unless you can get a direct comment from one of these people (which may not be as difficult a task as it sounds), then we have to wait until the end of the year (or the first quarter of next year) to find out.

But after investing all that time and expense on development, why wouldn't they deploy the Titan core?

> after investing all that time and expense on development, why wouldn't
> they deploy the Titan core?

I've no idea. I believe that in his amigaworld.net posting (which I quoted from back when we (as in you and me) still didn't know about the semi-official "Titan is dead" reports) minator implied that design partner Intrinsity having been purchased by Apple might have played a role. But maybe I'm reading too much into his comment. On the other hand, the Linley Group takes the same line: "Titan [...] ended up on the scrap heap when design partner Intrinsity was acquired by Apple".
And then there's the question as to what's been the original source for the July's "Titan is dead" reports. As far as I could research it was the Linley Group circulating this via their Microprocessor Report. But what's their source for this?
I mean how's that going along with Applied Micro top executives stating weeks later that the Titan core and the APM83290 chip based on that core will start generating revenue early next year which means that it must be in volume production already (not to mention their latest product roadmap including "Gemini")?

Update:

>> maybe Freescale rediscovers Altivec one day.

> I fear that won't happen.

Or maybe it will? From today:

"The aerospace and defense embedded computing industry is buzzing with rumors that Freescale Semiconductor Inc. in Austin, Texas, may be rethinking its commitment to AltiVec vector processing technology and its provision for floating-point processing in Freescale's latest family of QorIQ high-performance microprocessors. [...] The coming week may hold some interesting announcements, not only from Freescale, but also by some well-known embedded signal processing companies concerning the QorIQ and AltiVec. Stay tuned."
http://www.militaryaerospace.com/index/blogs/john-kellers-blog/blogs/military-aerospace/john-keller-blog/post987_1977664485155472586.html
http://milaero.blogspot.com/2010/09/freescale-may-be-rethinking-its.html

Maybe QorIQ T series will be announced to have AltiVec? Or even some new QorIQ P series member?

Quote:

Andreas, that would be ideal. PA Semi won't continue to offer their processor forever and Applied Micro's new offering still look at little weak (although much improved from past products).

Were Freescale to readopt AltiVec, they could strengthen the only weak point in their new 64bit processors.

> Applied Micro's new offering still look at little weak

You mean Titan/APM83290, which might or might not be dead? Or rather the yet to be announced new core/APM86xxx at 40nm? If the latter: do you have specs for this?

Quote:

That would be something indeed.

> That would be something indeed.

http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1474744

I can only congratulate Freescale on this exceedingly sensible decision.

More detail:

"Freescale [...] will incorporate its AltiVec vector processing technology into its multicore QorIQ microprocessor family later this year [...]. [...] Freescale will announce specific QorIQ microprocessor products announcements with AltiVec technology within the next few months"
http://www.militaryaerospace.com/index/display/article-display/6971313341/articles/military-aerospace-electronics/online-news-2/2010/9/altivec-floating-point.html


Edit:

Another nice article:

"new demands from multiple 4G users are now enabling wireless basestations to utilize SIMD. To meet the need, Freescale Semiconductor Inc. is upgrading its venerable AltiVec vector processing unit for its QorIQ family of Power Architecture-based communications processors. "Customers using QorIQ to deal with all the data being processed by 4G basestations are probably telling Freescale that the Altivec SIMD processor could be very useful at performing the same processing task [single-instruction] on multiple users [multiple-data]," said Linley Gwennap, principal analyst at The Linley Group (Mountain View, Calif.) [...] Freescale already sells legacy AltiVec processors to industry, military and aerospace customers performing traditional tasks such as image processing, pattern recognition and forward kinematics to position robotic arms as well as for emerging applications such as smart analytics on multiple surveillance cameras. But by adding AltiVec to its leading edge QorIQ processors, Freescale hopes to expand further its penetration of the basestation processor market. "We have taken a proven technology, enhanced it, and moved it to the multicore QorIQ family of processors," said Glenn Beck, marketing manager for aerospace, defense and single board computing within Freescale's Networking Processor Division. "We see a broad spectrum of applications that are now needing vector-caliber performance, ranging from networking and telecom to the classic ones in aerospace and defense." [...] With an AltiVec inside each QorIQ core, an additional eight parallel floating-point and integer processing units execute vector algorithms using 180 instructions."
http://www.eetimes.com/electronics-news/4208818/Vector-processing-accelerates-QorIQ2

[ Edited by Andreas_Wolf on 2010/9/28 19:16 ]

Update:

>> Applied Micro's new offering still look at little weak

> You mean Titan/APM83290, which might or might not be dead? Or rather the yet to
> be announced new core/APM86xxx at 40nm? If the latter: do you have specs for this?

I guess we know the specs by now. From today's press release:

"The AppliedMicro PacketPro family features performance of up to 2 GHz per core, 32KB L1 I/D & 256KB dedicated L2 cache per core, support for full symmetric multiprocessing (SMP) and ultra flexible asymmetric multiprocessing (AMP). Memory and bus architecture supports 16/32/64-bit DDR2/3 up to 1,600Mbps and beyond with ECC option. Connectivity features include PCI-e Gen 2 controller, GE, 10GE, SGMII, RGMII, IEEE1588 Rev2 on all Ethernet ports, USB 2.0 - H/D, OTG, all with integrated PHY, USB 3.0, SATA ports and SDHC. The PacketPro family is manufactured on a 40nm TSMC(R) CMOS process and is available in both wire-bond and flip-chip packaging. The first PacketPro device begins sampling in November."
http://investor.appliedmicro.com/phoenix.zhtml?c=78121&p=irol-newsArticle&ID=1474906

From the product page:

"PACKETpro is AppliedMicro's second-generation of embedded multi-core processor SoCs and the first to feature expandability from one to eight 32-bit PowerPC 465 cores ranging in performance from 600 MHz to 1.5 GHz."
http://www.appliedmicro.com/products/process.html#EmbeddedProcessors

From the product info PDF file:

"PACKETpro is AppliedMicro's second-generation of embedded processor SoCs and the first to feature expandability from one to eight 32-bit PowerPC 465 cores ranging in performance from 600 MHz to 2.0 GHz."
http://www.appliedmicro.com/products/apm_pp_web.pdf (page 2)

Page 4 shows an interesting chart listing three CPU generations:
- past: single core, 32 bit, 1.5 GHz (PPC464 core based 1.4 GHz PPC460SX/PPC460GTx)
- today: multicore, 32 bit, 2.0 GHz (PPC465 core based PacketPro processor)
- future: multicore, 64 bit, 2.5 GHz (Viper?)

Titan/APM83290/"Gemini" doesn't seem to fit any of these generations, indicating that it's rather dead than alive.

My observations/questions:
1. Does PacketPro have an FPU?
2. They don't seem to be sure if PacketPro is 1.5 or 2.0 GHz.
3. PacketPro is PPC465 based, which explains the "465" being listed as "32-bit Commercial Core" of Applied Micro in Power.org's latest Power Architecture roadmap version.
4. PacketPro obviously doesn't use a "40nm variant of their Titan core".
5. What is Applied Micro's "Next-gen" "32-bit Commercial Core" that is listed in Power.org's latest Power Architecture roadmap version? Is it Titan?
6. What is Applied Micro's "APM86XXX" "32-bit Commercial Processor" that is listed in Power.org's latest Power Architecture roadmap version? Is it PacketPro?

What's also a nice destail in this news item is that Freescale does not list the network and telecomunications as target only but also medical, military, printing, robotocs and video systems.
My impression was that QorIQ was yet marketed as powerQUICC replacement which more or less targeted the network/telco market only.
Let's see how this develops...

> What's also a nice destail in this news item is that Freescale does not
> list the network and telecomunications as target only but also medical,
> military, printing, robotocs and video systems.

I guess that networking and telco is the target application of present QorIQ (i.e. without AltiVec), while coming QorIQ with AltiVec will (also) target the other fields (like MPC86xx to date).

> My impression was that QorIQ was yet marketed as powerQUICC replacement

As I told you already, Freescale's Power Architecture roadmap has explicitly been painting the QorIQ P4 and P5 chip families as replacements for the MPC86xx chip family. QorIQ P1 to P3 is supposed to replace PowerQUICC I to PowerQUICC III. At least that's what the roadmap presentation depicts.
It seems that Freescale has come to realizing that chips without AltiVec aren't quite adequate as replacements for chips with AltiVec. Future QorIQ chips with AltiVec will be regarded by 3rd parties as the real de-facto MPC86xx successors, as opposed to the presently announced/available QorIQ P4 and P5 chips without AltiVec which are regarded by 3rd parties only as "de-jure" successors to the MPC86xx, if at all.

> which more or less targeted the network/telco market only.

By far not all PowerQUICC chips even have the QUICC engine. I guess that's part of Freescale's intention to deliberately confuse (potential) customers ;-) PowerQUICC as a whole not only targets network/telco but also imaging/video, (multifunctional) printing, industrial control/robotics, measurement, storage and even military.


I wonder if Freescale will implement AltiVec in QorIQ
a) as a sub-unit of e500/e5500 core (like with e600) and thus create new core(s) or
b) as a coprocessor unit to e500/e5500 core or
c) simply by taking e600 core and continuing its development (i.e. e600 based QorIQ) ;-)

Yes, Freescale's marketing can be confusing, but its not nearly as vexing as Applied Micro's product information.

And I'm completely confident that Freescale will release the products they announce. Applied Micro on the other hand seems to regularly announce products before they're even assured that they will be produced.

Think about it, who has more credibility Freescale who inherited Motorola's CPU production technology or Applied Micro who licensed low end IBM designs?

> I'm completely confident that Freescale will release the products they announce.

You mean like the MPC75xx or the MPC87xx (e700 core)? ;-)

> Applied Micro on the other hand seems to regularly announce products
> before they're even assured that they will be produced.

The most confusing thing is that they said that Titan/APM83290 samples had been in the hands of (selected) customers who successfully validated the chip for their products, which is for about a year now:

------------------------------
Paramesh Gopi: I am extremely pleased to report that we are sampling 1.5 GHz multi-core SMP devices in an extremely cost optimized TSMC 90 nm node. [...] Our current TSMC core has garnered a tremendous amount of interest in the document processing and control processor segments and we look forward to reporting upcoming wins at major tier 1 OEMs as they materialize. [...] We are sampling the world's first TSMC-based dual core SMP 1.5 GB [sic!] power architecture SoC.
[...]
Robert Gargus: [...] I just want to caution you that this is a chip that we have just begun sampling. So it's not yet really into production and generating revenue. It's probably still a couple of quarters, two to three quarters away from starting to generate any kind of meaningful revenue on our P&L. But the amount of interest--and if you want, customer interaction on the chip is very encouraging at this point in time.
[...]
Allan Mishan: Hey Guys, quick question on the Titan products. You specifically mentioned document processing and control plane as areas where you're targeting now. Are you also offering Titan to all the other applications where you've historically worked with the IBM products as well or really are those two the priorities in the near term?
[...]
Robert Gargus: I think the ones we mentioned are just the ones that we can point to in terms of design activity that's going on currently. But over time, we expect to have that chip find its way into many, many more places.
------------------------------
http://www.sec.gov/Archives/edgar/data/711065/000119312509223997/dex992.htm (transcript of Applied Micro's second quarter 2010 earnings conference call in late October 2009)

------------------------------
Paramesh Gopi - Applied Micro Circuits Corporation - President, CEO
[...] we are extremely pleased with the reception of our TSMC-based 1.5 gigahertz multicore SMP device. We have secured the first of a series of SoC design wins in Tier 1 enterprise document processing systems. The integration of power-efficient cores in an established mature TSMC process node, coupled with our industry-leading packet processing IP and DSP subsystems, enable highly efficient implementations of image pipes, as well as network document and video processing functions. This has firmly established us as the leader in providing multicore, power efficient, multi-gigahertz cores to a wide customer base. We expect to announce meaningful revenue in 2011 resulting from these designs. Additionally, we are pleased to report that the validation of our cores at major customers sets the stage for our migration to 40 and 28 nanometer process nodes, and ensures that our core technologies are fully scalable. [...] Power architecture has never had the same accessibility as other architectures in very normal vanilla CMOS processes. So a lot of the initial barrier was nobody believed us. There was a huge amount of skepticism as to whether we would even get a gigahertz core at a process node that was 90 nanometer, much less anything that is 65 or 40. The uniform feedback was, you guys have shown us slides for three years, make us believe it. So I think I would say the last six months have proven beyond doubt that there is no more uncertainty in us being able to develop, sample, validate and drive our internal core architecture into the market. [...] So we have pretty much proven that there is a secret sauce and it has been a lot of work, but I think very few companies in this world can boast of a gigahertz plus architectures, especially in the PowerPC space in a TSMC process. So I think where we have established that beyond doubt that we can execute that. So now it is a matter of essentially driving that into real business. And that process has started very, very nicely in earnest with our key customers. As they see performance and they see cost and they see the scalability to do the 4 to 6 to 8, I mean, it is a full SMP-capable core and interconnect subsystem, so it is all there.
------------------------------
http://www.sec.gov/Archives/edgar/data/711065/000119312510020952/dex992.htm (transcript of Applied Micro's third quarter 2010 earnings conference call in late January 2010)

------------------------------
Paramesh Gopi - Applied Micro Circuits Corporation - President, CEO
[...] we also had success in the enterprise market where we won a Tier 1 cost-optimized wireless access point designed for the China and India markets. This was enabled once again by our cost-optimized, customized, power-efficient multicore technology being brought to a new cost point. Overall, I'm extremely pleased with our penetration into our target segment and our overall design execution.
------------------------------
http://www.sec.gov/Archives/edgar/data/711065/000119312510109166/dex992.htm (transcript of Applied Micro's fourth quarter 2010 earnings conference call in late April 2010)

So the question is: What went wrong? Is it really due to Intrinsity's acquisition by Apple as some suspect? On the topic of Apple/Intrinsity I only found the following from the April 2010 conference call:

------------------------------
Robert Gargus - Applied Micro Circuits Corporation - SVP, CFO
[...] Following the end of the quarter, a company where we had an equity investment was acquired by Apple. As a result of this transaction, we realized the full value of our investment, which was approximately $5.4 million. We received this cash earlier in the month. [...] The $206.6 million cash balance excludes [...] the $5 million received in the first week of April upon the sale of our equity investment to Apple.
------------------------------

> who has more credibility Freescale who inherited Motorola's CPU production
> technology or Applied Micro who licensed low end IBM designs?

I think they both have plenty of skeletons in their respective closets.

Personally, I can't really hold Freescale's failure to pursue the e700 core against them. It reminds me of Motorola and the 68K. I was really into that family line (and when the 68030 came out I was convinced it was going places). Motorola did forge ahead with the 68060 (an incredible processor) even after losing a huge part of its market.
If it doesn't sell, you've got to move on. The e600 series did not sell well and like the 68060 that spelled doom for a future successor.
Freescale's current shift in marketing merely reflects what they think will be profitable.

When Applied Micro actually lets someone see some of this mythical silicon, then I'll start to place more faith in their press releases.