> I actually did mean 86XX

Okay. To relate to the point what Freescale thinks the target market for the e600 based MPC86xx has been, we shouldn't forget that the MPC74xx has always been used also in the embedded area, not only as CPU for Apple. So we can assume that the target market for the MPC86xx, which is the MPC74xx's successor, stayed the same. But let's not just assume, but rather see what Freescale says:

MPC8610:
"embedded applications that process or display graphical images, such as kiosks, robotics, in-vehicle infotainment, cockpit displays, single-board computers and multi-function printers and scanners"

MPC8640(D):
"embedded networking, telecom, aerospace and defense, storage, industrial and pervasive computing applications"

> as they are still available after Apple's departure

Actually, they started being available only after that. The first one of the series, the MPC8641(D), was announced in 2004, i.e. before Apple's switch announcement, but began sampling only in 2006.

> but are now somewhat pointless with the introduction of the P5

I wouldn't say so. The markets the MPC74xx and later the MPC86xx have been aimed at heavily rely on the capability of AltiVec code execution (or SIMD processing in general, with AltiVec being preferred for code reuse reasons). That's why the current QorIQ P series is not considered an adequate MPC86xx replacement by customers from those industries, albeit Freescale wishing it would. To compensate for that and not lose too many customers to Intel and its SSE and AVX capable processors, Freescale did what you know they did: announce the availability of AltiVec for future QorIQ processors. They wouldn't have done that if they had been able to avoid it. As soon as QorIQ with AltiVec will be there, MPC86xx will be rather pointless, yes. But so far, if you want AltiVec then MPC86xx is a viable option. More there:

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7001&start=455

> I've rarely seen the X700 cored products

It's e700 ;-)

> refereed to as MPC87xxs (although that is what they would
> have likely been called).

Likely? 'MPC87xx' is the moniker Freescale used to refer to the e700 core based processors in their presentations and roadmap depictions. Just explore the documents linked from those Google results:

http://www.google.com/search?q=%22mpc87xx%22+freescale
http://www.google.com/search?q=%22mpc87xx%22+%22e700%22

There's even still one PDF file online on the Freescale website (page 6):
https://web.archive.org/web/20190825104155/https://www.nxp.com/docs/en/application-note-software/1033_e300_e500_e600_comp.pdf

Unfortunately, most of the old Freescale documents mentioning the MPC87xx are not online anymore and thus not indexed by Google anymore. (But don't be confused by some of the results as it seems there was an 'MPC87xx' already on Motorola's 2001/2002 roadmaps, but that was another thing altogether.)

> Were there any real details (let alone prices)?

I'm only aware of the details I listed in my previous posting. And as I said, I don't think there were any prices mentioned.


Edit: updated some URLs

[ Edited by Andreas_Wolf 20.01.2026 - 12:24 ]

Thanks for getting me what you could.
And you're right, until the T5 replaces the P5
Then the product will have AltiVec.


Plus, the MPC8641 has more PCIe lanes (although only 1.0) and PCI slot capability.

But the speed advantage of the P5 and the future introduction of AltiVec makes this the processor to look out for.

The e600 is dead.

> the MPC8641 has more PCIe lanes (although only 1.0)

Yes, it can dedicate up to 16 SerDes lanes (x8 x8) to PCIe. But as you say, that only equals 8 lanes (x4 x4) when compared to the QorIQ P5's PCIe 2.0. So overall, the QorIQ P5 can dedicate up to 50% more bandwidth to PCIe than MPC8641(D), or up to 25% more bandwidth in a configuration suited for desktop computing (i.e. with on-chip SATA controllers enabled).

> and PCI slot capability.

Neither MPC8641(D) nor MPC8640(D) incorporate a PCI controller. Do you mean the MPC8610 here maybe?

> The e600 is dead.

...as soon as the AltiVec enabled QorIQ T is there, yes. Regardless, Freescale will offer the existing MPC86xx chips for quite some years to come.

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=7001&forum=3&post_id=80669#80669

>> and PCI slot capability.

When used with a Southbidge a MPC8640/8641 design can incorporate PCI slots.

> When used with a Southbidge a MPC8640/8641 design can incorporate PCI slots.

Yes, but so can a QorIQ P5 design (and any other design based on a chip with an interface a southbridge can be attached to), so that's no difference between the two. And of course it doesn't need a southbridge chip for this. A PCIe-to-PCI bridge chip would do well. With the QorIQ P5 in x4 x4 x1 x1 PCIe configuration you could use one x1 to bridge to a PCI slot.

Interesting idea though. An SB800 Southbridge would cost us four PCIe 2.0 lanes, but would also supply four PCie lanes.
Which configuration was it that you said we lost SATA controllers?

> An SB800 Southbridge would cost us four PCIe 2.0 lanes,
> but would also supply four PCie lanes.

According to the 'AMD SB810/850 Southbridge Databook' there're only two PCIe 2.0 lanes supplied, not four:

http://support.amd.com/us/Embedded_TechDocs/44758.pdf (page 12)

> Which configuration was it that you said we lost SATA controllers?

The one you liked most ;-)

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=7183&forum=3&post_id=82381#82381

So let me summarize the two options:

1. without southbridge:
- SATA controllers on P5 must be enabled, thus x4 x4 x1 x1 PCIe config is best
- use one x1 with bridge chip to get legacy PCI slot
- for audio there're those options to select from:
-- sound card in legacy PCI slot
-- sound card in PCIe x1 slot
-- on-board audio chip on PCIe x1
-- nerdy: use P5's SPI bus with a CPLD acting as SPI-to-I²S bridge and connect an audio chip via this I²S ;-)
- one x4 for graphics card
- leaves one of the following PCI(e) connection configs for use at will: x4+x1 or x4+PCI or x4+x1+PCI

2. with SB800 southbridge:
- don't need P5's SATA controllers, thus x4 x4 x4 PCIe config can be used
- use one x4 to attach SB800
- legacy PCI provided by SB800
- audio provided by SB800
- additional two PCIe lanes provided by SB800, either two x1 or one x2
- one x4 for graphics card
- leaves one of the following PCI(e) connection configs for use at will: x4+x1+x1+PCI or x4+x2+PCI

Great summary Andreas. I hadn't even had a chance to go over this yet (and now I don't have to).
The Sb800 SATA controllers are 3.0. What are the P5s?

With an SB800 series Southbridge we also gain additional SATA controllers (six total).

Very interesting comparison.
W/O SB - X4+X4+X1 PCIe 2 SATA
W SB X4+X4+X1+X1 PCIe 6 SATA and PCI

[ Edited by Jim on 2011/3/21 4:46 ]

[ Edited by Jim on 2011/3/21 11:04 ]

> The Sb800 SATA controllers are 3.0.

On SB850, yes. SB810 has only 2.0.

> What are the P5s?

2.0.

> Very interesting comparison.
> W/O SB - X4+X4+X1 PCIe 2 SATA
> W SB X4+X4+X1+X1 PCIe 6 SATA and PCI

The question is whether those benefits of having the SB800 would really be worth the additional costs.

[ Edited by Andreas_Wolf on 2011/3/21 17:04 ]

Yes, this isn't like the MPC8641, where if you didn't use a Southbridge you didn't have certain peripherals.
The P5 is fairly complete without the Southbridge. It would bring us PCI slots for legacy hardware. It doesn't actually cost us any PCIe expandability (we actually we gain one X1).

And we gain several SATA controllers and sound output. You must admit that two SATA controllers is somewhat limited.

But it does add cost and complexity. You can already guess what side my opinion falls on, but the simpler option might be the more sensible one.

> (we actually we gain one X1). And we gain [...] sound output.

Here I think you counted one and the same thing twice. *Either* the SB800 gains us audio (but no additional PCIe) *or* it gains us one x1 (but no audio over the other solution with dedicated audio chip or card on x1).

> You must admit that two SATA controllers is somewhat limited.

For me personally, two SATA controllers would be sufficient.

> the simpler option might be the more sensible one.

I second that.

Well, we should be able to add an additional SATA controller via the X1 PCIe lane.

Frankly, I wouldn't find 2 SATA controllers adequate.

With one SATA connection used for DVD, that only leaves us one connector for a hard drive. I'd prefer at least two.

But we can probably flesh out a complete system without a Southbridge.

OK Andreas, how long do you think it will be before we can get specifications on the P5 that are as good as those you referenced on the SB810/850?
Also, would it make more sense to go for a P5010 based system or one based on the P5020?

> how long do you think it will be before we can get specifications
> on the P5 that are as good as those you referenced on the SB810/850?

Somewhen in the course of this year, I guess.

> would it make more sense to go for a P5010 based system or
> one based on the P5020?

That would depend on the price difference between the two.

Update:

> the annual Freescale Technology Forum. The titles of this year's
> technical sessions have already been published:
> [...]
> "Using Freescale's AltiVec SIMD Engine for Graphics, Image Processing,
> Radar, Video Surveillance and Other Applications"
>
> They didn't have sessions on AltiVec for some years. I guess this is going
> to be a foretaste of AltiVec-enabled QorIQ T.

Detailed descriptions of the sessions are online:

http://www.getregisterednow.com/FSL/CEX/Session.aspx?li=1

From there:

"During this session, attendees will gain insight into the next-generation QorIQ products that provide heterogeneous cores, AltiVec-enablement and assured computing with significant overall system performance within embedded power budgets." (FTF-NET-F0273)

"AltiVec technology, the SIMD accelerator on current e600 core microprocessors, has found a home on the QorIQ processor roadmap and has proven useful in graphics, image processing, printing, radar, sonar, video surveillance and other markets. This presentation will look at some of the performance enhancements achieved with original AltiVec technology and the improvements incorporated in the updated version." (FTF-NET-F0531)

I'm really eager to see what those "improvements incorporated in the updated version" of AltiVec are about. That goes in line with what Glenn Beck, marketing manager for aerospace, defense and single board computing within Freescale's Networking Processor Division, said when he divulged six months ago that with AltiVec they "have taken a proven technology, enhanced it, and moved it to the multicore QorIQ family of processors". I hope it will be better than IBM's VMX128.

Edit: PDF presentation with mention of "Enhanced AltiVec" (page 8):

http://www.advantech.eu/adf/file/munich/agenda/Advantech_Design-In_Forum_QorIQ.pdf

[ Edited by Andreas_Wolf 14.04.2011 - 14:44 ]

Man you're willing to dig to find info.

Three days and 1 one hour session.
FTF-NET-F0531 Thursday 09:00 1 hour Salon F

I dug through a lot of those sessions and the one you quoted is one of the few I'd have any interest in.

Why don't we just contact Bill Mercer after the event and see if he can offer a summary?

> Three days

It's four days, Monday through Thursday.

> the one you quoted is one of the few I'd have any interest in.

Let me guess the others: FTF-NET-F0394 and FTF-NET-F0399. Correct? :-)

> Why don't we just contact Bill Mercer after the event and see if
> he can offer a summary?

We won't have to do that as Freescale will offer all presentation slides for public download, as usual.

>We won't have to do that as Freescale will offer all presentation slides for public download, as usual.

Now you have my attention, sir!
Yeah! Hard info on the T5!

Update:

> 1.5 weeks ago A-Eon changed the X1000's official specs from 1.8 GHz to 2.0 GHz.

3.5 weeks ago they changed it to "nominal 2.0GHz (1.8GHz standard)".

http://www.a-eon.com/x1000.html

It could mean that it is supposed to be delivered underclocked at 1.8 GHz with heatsink but without fan and that the user who wants to run it at nominal 2.0 GHz speed would have to add a fan himself. Assuming this suspicion is true would leave one question though: If the usage of the extra 200 MHz of *one* core should require the addition of a fan what's with the usage of *both* cores at 1.8 GHz, e.g. under Linux?

Quote:

actually the right translation is "PA Semi only took an architectural licence from IBM"

some twisted french syntax

>> Google translation:
>> "PA Semi did not take an architectural license from IBM"

> actually the right translation is "PA Semi only took an architectural licence from IBM"

Thanks for clarification. I put way too much faith into Google it seems ;-)

Addendum:

> I guess there're still some information to be revealed to get the whole "quite a story".

A-Eon didn't reveal it so far (no idea why), but as there're still discussions on this and questions occuring at various places I'm going to tell how I perceive this "quite a story" came along in chronological order:

1. A-Eon decides for the PA6T, approaches P.A.Semi for recommendation of a board design company with PA6T experience and subsequently get turned to Varisys.
2. A-Eon plans on buying PA6T chips from P.A.Semi, but before it's able to place an order P.A.Semi is purchased by Apple (April 2008).
3. Apple decides to supply the PA6T to P.A.Semi's existing customers only, which A-Eon is not but Varisys is.
4. Apple calls P.A.Semi's existing customers for final PA6T orders as the chip is going to be discontinued. Varisys informs A-Eon about this call.
5. A-Eon asks Varisys to place an order for an (unknown to us) amount of PA6T chips. Varisys agrees.
6. Varisys orders the chips from Apple. The chips arrive at Varisys.
7. A-Eon in turn purchases those chips from Varisys, effectively rendering Varisys A-Eon's CPU supplier (the chips remain at Varisys, though, for obvious reasons). As part of this supply agreement between Varisys and A-Eon, Varisys demands an NDA* to be signed.

* The reason for Varisys' NDA requirement is even more speculative than my timeline. Maybe the supply agreement between Apple and its PA6T customers contained the condition that the customer must not resell the chips to 3rd parties, which is what Varisys effectively did though, so they feared penalty from Apple. It's odd at least that Varisys was officially revealed as A-Eon's design partner in June 2010 while the exact type of CPU was only officially revealed half a year later (which must be when the NDA ended).

Addendum:

> > would it make more sense to go for a P5010 based system or
> > one based on the P5020?

> That would depend on the price difference between the two.

No prices on the P5 yet, but seeing the price difference the number of cores makes with the P4 going for the P5010 could be a sensible decision:

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=11&topic_id=6196&start=160

With the P4 halving the amount of CPU cores cuts off chip price by 25%. Don't know if Freescale will apply this policy also to P5 though.

>A-Eon didn't reveal it so far (no idea why), but as there're still discussions on this and questions occuring at various places I'm going to tell how I perceive this "quite a story" came along in chronological order:

Everyone should keep in mind that Andreas is probably right about this sequence of events (in fact, his explanation is the only on that fits the facts), but this is still speculation.

Obviously, for the reasons stated in Andreas' summary, Trevor and the rest of A-eon haven't been able to reveal some of this information.

> Obviously, for the reasons stated in Andreas' summary,
> Trevor and the rest of A-eon haven't been able to reveal
> some of this information.

Really? Could you name those reasons? I ask because as I stated above I've "no idea why" some of those information should still be confidential when the NDA between Varisys and A-Eon had ended in (or before) December 2010 obviously.