>>> Currently the A9 is in PPC G4 territory performance wise.

>> which clock rate in G4 do you think a 1.2 GHz (which I think is the
>> current max) Cortex-A9 roughly resembles performance-wise?

> I believe they're quite similar clock for clock.

Also here, found some NBench figures of both to compare.

Cortex-A9: http://www.powerdeveloper.org/forums/viewtopic.php?p=14836#14836
G4: http://amigadev.free.fr/powerpc/nbench.html

Result scores (for 1.0 GHz each):

Cortex-A9 (one core of dual-core OMAP4):
- MEMORY: 6.52
- INTEGER: 6.19
- FLOATING-POINT: 6.82
- BYTEMARK INTEGER: 25.4
- BYTEMARK FLOATING-POINT: 12.3

G4 (scaled from 400 MHz | scaled from 1.4 GHz | scaled from 1.5 GHz*):
- MEMORY: 7.49 | 5.76 | 4.49
- INTEGER: 6.69 | 8.27 | 5.76
- FLOATING-POINT: 9.24 | 6.47 | 9.02
- BYTEMARK INTEGER: 20.7 *
- BYTEMARK FLOATING-POINT: 16.3 *


* my machine

Nothing too surprising there. I do expect the G4 will be better at floating point - FP has never been ARM's strong point (the Cortex-A15 should be a lot better).

That said a 15 year old benchmark is probably not a great test - can you run CoreMark?

> can you run CoreMark?

I guess it could be compiled and made to run on Leopard. But that requires registering with EEMBC, which I won't do.

Update:

> I'm not sure Krait based chips are really sampling at 2.5 GHz
> already. Some sources say the MSM8960 will only clock up to
> 1.2 GHz and it will take until the APQ8064 to actually reach 2.5 GHz

New info:
http://www.mobiletechworld.com/2011/07/05/new-qualcomm-2011-2012-roadmap-and-soc-specifications/

Apparently, my doubts were justified and 2.5 GHz Krait will indeed not come until APQ8064 scheduled for 2012 at earliest, but MSM8960 scheduled for Q4/2011 is intended to clock between 1.5 and 1.7 GHz, not just 1.2 GHz which was claimed by the source I quoted.

Update:

>> Probably the fastest ARM around right now CPU and GPU wise

> Yes, it's 20% higher clocked than the SoC on the Snowball board

Apparently, they decreased clock frequency from the annnounced 1.2 GHz to only 1.0 GHz as well:

"Samsung Exynos4210 Cortext-A9 dualcore 1.0GHz"
http://www.origenboard.org/about.php

> http://www.raspberrypi.org/ [...]
> More tech details, performance and such would interesting though.

The SoC has just recently been revealed as the BCM2835:

http://www.raspberrypi.org/?p=106
http://www.raspberrypi.org/?page_id=43&mingleforumaction=viewtopic&t=36.3

In other news, this is from GlobalFoundries:

Quote:

Full story here.

> Video of this 7 days old silicon here: http://www.youtube.com/watch?v=p0lkZlDTq8Q

"Freescale unveiled its i.MX 6 product family in end-June, and revealed the new processors are available in sample and volume quantities."
http://www.digitimes.com/news/a20110831PD212.html

From first silicon to volume production in 11 weeks? Doesn't sound like Freescale at all to me ;-)

Update:

>>> does the A2 have AltiVec/VMX?

>> Don't know but they could always add it.

> Yes, of course they could, but what I would like to know is
> whether IBM's stock A2 core (as used in the PowerEN and
> Power BQC chips) has it. I ask because I've read conflicting
> third party statements on that matter (and no statement by IBM itself).

http://www.theregister.co.uk/2011/08/22/ibm_bluegene_q_chip/

As that detailed article doesn't mention AltiVec/VMX for the A2 core I assume that it's not there.

Update:

> I compiled a small list of DMIPS per MHz and core figures for various
> recent and future cores implementing ARM ISA:
>
> ARM Cortex-A8: 2.0
> Qualcomm Scorpion: 2.1
> Marvell Sheeva PJ4: 2.4
> ARM Cortex-A9: 2.5
> Qualcomm Krait: 3.0...3.5 (estimated)
> ARM Cortex-A15: 3.5 (estimated)

"A new pipeline architecture increases the performance of Krait by over 60% compared to Qualcomm's existing Scorpion CPU micro-architecture."
http://www.qualcomm.com/documents/files/snapdragon-s4-processors-system-on-chip-solutions-for-a-new-mobile-age-white-paper.pdf (page 3)

Going by that, Qualcomm's Krait core could deliver as much as about 3.4 DMIPS per MHz and core.

Quote:

You missed the Cortex-A7

> You missed the Cortex-A7 ;-)

I surely didn't miss ARM Ltd's today's announcement of the Cortex-A7 core :-) The reason it's not been on my list yet simply is that I hadn't read about the DMIPS figure for it. Doing so now I can see that it's as low as 1.9 DMIPS per MHz and core (and the figure for the Krait core is in that article as well). So this is the new revised list:

ARM Cortex-A7: 1.9
ARM Cortex-A8: 2.0
Qualcomm Scorpion: 2.1
Marvell Sheeva PJ4: 2.4
ARM Cortex-A9: 2.5
Qualcomm Krait: 3.3
ARM Cortex-A15: 3.5 (estimated)

Update:

> "T50/Tegra 5 is now known as Denver, but the x86 part has been dropped for legal reasons."
> http://semiaccurate.com/2011/04/06/nvidia-in-full-philosophical-retreat-for-tegra-3/

More on what Project Denver has/had to do with x86:

"T50 was going to be a full 64-bit x86 CPU, not ARM cored chip, but Nvidia lacked the patent licenses to make hardware that was x86 compatible. [...] Publicly, Nvidia's stance was that there was no need for any license because the company was not making x86 hardware. Technically, this is true, T50 is a software/firmware based 'code morphing' CPU like Transmeta. The ISA that users see is a software layer, not hardware, the underlying ISA can be just about anything that Nvidia's engineers feel works out best. T50 is not x86 under all the covers, nor is it ARM, it is something else totally that users will never be privy to. The idea was that this emulation of x86 in software would be more than enough to dodge any x86 patents that would stop the chip from coming to market. SemiAccurate has it on very good authority that this cunning plan would not have succeeded, and based on what the sources showed us, the chip never would have gotten to market. [...] So, where does a core go from here? That one is easy, it becomes an ARM core, or if you believe Nvidia PR, it was ARM all along. T50 was never ARM hardware based, we had originally heard it was an A15 or the follow-on part, that emulated x86, that information turned out to be wrong. T50 is its own unique ISA, and emulates the exposed ISA as embedded software. Think of it as an on chip x86 or ARM compiler to the low level instructions. So, between last fall and CES, out went x86, and in came ARM, specifically the ARM-64 core that is the follow up to the A15 chip."
http://semiaccurate.com/2011/08/05/what-is-project-denver-based-on/

Well, Transmeta reloaded then. Fine, and who developes a "Power compiler" for T50 then ?

Quote:

"The ARM Cortex™-A7 MPCore™ processor is the most efficient application processor ARM has ever developed and dramatically extends ARM’s low-power leadership in future entry level smart phones, tablets and other advanced mobile devices.
The architecure and feature set of the Cortex-A7 processor are identical to the Cortex-A15 processor, with differences in the Cortex-A7 processor's microarchitecture focused on providing optimum energy efficiency, enabling the two processors to operate in tandem in a big.LITTLE configuration to provide the ultimate combination of high-performance with ultra low power consumption.

As a standalone processor, the Cortex-A7 will enable entry level smartphones at below $100 price point in the 2013-2014 timeframe that are equivalent to a $500 high-end smarphone in 2010. These entry level smartphones will redefine connectivity and internet usage in the developing world."
http://www.arm.com/products/processors/cortex-a/cortex-a7.php

Sounds *very* interesting IMHO! This one together with the Cortex-A15 becomes the new ARM "dynamic duo"!

Quote:

Quite literally - read up on the "big.little" tech that Freescale licensed:

http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1619038&highlight=

Quote:

So if I read this correctly, they plan on putting one Cortex-A7 core in the same physical chip as one (or more) Cortex-A15 cores, and then either of these can seamlessly be powered up/down and be "taking over the show", depending on performance needs contra power consumption?

Sounds a bit complicated, but very interesting!

> if I read this correctly, they plan on putting one Cortex-A7 core in the
> same physical chip as one (or more) Cortex-A15 cores, and then either
> of these can seamlessly be powered up/down and be "taking over the
> show", depending on performance needs contra power consumption?

Yes, that's exactly what this "big.LITTLE configuration" the quote from ARM Ltd. in your previous posting is talking about means (except that it's two Cortex-A7 cores, not one). See:

http://www.arm.com/products/processors/technologies/bigLITTLEprocessing.php
http://www.arm.com/files/downloads/big.LITTLE_Final.pdf

Adding low-power core(s) for lower overall power consumption is by the way a popular concept in ARM land:

http://www.marvell.com/company/news/pressDetail.do?releaseID=1486
http://blogs.nvidia.com/2011/09/quad-core-kal-el%E2%80%99s-stealth-fifth-core-lets-it-save-on-energy/
http://www.ti.com/ww/en/omap/omap5/omap5-OMAP5432.html
http://www.ti.com/ww/en/omap/omap5/omap5-OMAP5430.html

Quote:

It's configurable, you can have 1 - 4 A7s with 1 - 4 A15s or various combinations thereof.

Quote:

Using a smaller core to do a specific task is nothing new.
The most similar idea is Nvidia's but their system doesn't appear to be cache coherent so you have to flush the caches when switching between cores.

The big-little system is cache coherent so is a lot faster and doesn't require cache flushes. The switching can also be done at the hypervisor level so the OS doesn't even know it's happened.

The Nvidia also only uses a lower power A9 rather than the much lower power A7.


What's going to be interesting is how Intel are going to respond to this. Their super 22nm FinFET process was meant to get them down to ARM's power levels. That might happen compared with the A15 but the A7 is a complete different ball game, they don't have anything to compete with it.

>> except that it's two Cortex-A7 cores, not one

> you can have 1 - 4 A7s

I stand corrected then. Thanks for the info.

> Using a smaller core to do a specific task is nothing new.

Yes, I know that.

> The most similar idea is Nvidia's but their system doesn't appear to be
> cache coherent so you have to flush the caches when switching between
> cores. The big-little system is cache coherent so is a lot faster and doesn't
> require cache flushes. The switching can also be done at the hypervisor
> level so the OS doesn't even know it's happened.

Yes, ARM Ltd's "big.LITTLE Processing" concept is without doubt the most sophisticated one compared to the concepts currently being implemented by nVidia, TI and Marvell.

> when this guy gets so much PR with his 25$ ARM stick, maybe it would be
> worthwhile to do something similar (probably a little bit more expensive
> though) with the 5125? [...] I would join such an effort immediately.

"I [...] still have a project ongoing with an e300/400 based processor (5125)."
http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=34459&forum=33&start=240#634260

Has anything happened in the last 5 months you might want to share? :-)

Quote:

There's not much to share yet, but I am working on something - though not at a high pace or with a high priority (yet). I am still open for ideas, know how, a helping hand, whatever, #?.

Definately keep us in the loop Zylesea.
Right now I'm looking at the P5010/5020 as a way of understanding how the T5s will work.

But any project based on the T5 would be complicated and expensive.

Applied Micro (aka AMCC - the company that does the CPUs in the Sam 440 and 460) have announced a new processor.

You were probably not expecting this

Though not directly relevant for the MorphOS world this is an interesting approach. A basis for rather cheap and energy efficient highly parallel systems - could work out well for Applied Micro.