Nice thinking about a dual G5 Machine or maybe
a G6 or G7 or ???? maybe bee happy with a
PEG2 working and a upcoming Morphos 1.5

please

i think it is a little early to be thinking about the G7 as well as the G6 are wayyy far away as far as an actual release...

I agree with Maurix, at least a G5. That would put us on the 'cutting edge' so far.

Harry

Honestly speaking, I really want up-to-date software instead of speed increase with MorphOS. But hey, ofcourse a G5 would be nice to have

Bye,

Spidey

First I would like to see more quality apps for MorphOS not only quick and dirty ports. Then we can talk about faster CPUs. A G5 is a bit useless if there are no apps that could take advantage of it.

Pegasos G5: Oracle announces MorphOS support? Just kidding :)

G6 and G7 are not even out yet, so it is not a good thing to base an entire product on that. G5 however would be a very very good idea. I think a G5 product would also stay rather long at the top of the line, or not much below it.

Why do I think that? Chips speed will not increase as fast as it used to, only parallellising right now (like in the Cell chip or with dual core chips) would be able to gain you some fast advancements. But the gains in most areas of parallellising (except matrix multiplication - like used in 3D and other streaming media) will diminish with increasing number of "processors".

Basically we see that in the chips industry there is a turning point. Moores law can no longer be maintained, and die shrinks do not gain as much as they used to because of additional complications. Things have to be done differently, and that costs a lot of extra for the companies who produce these chips (or the machines to build them). For example we see that with a transistor shrink from 90 to 60 nm the gates built using silicon dioxides as isolators become susceptive to current tunneling. Since tunneling goes with an exponential function of distance between the gate and the part where current flows, you must make the gate isolator "longer" to reduce tunneling. For this you need a higher k material like siliconoxinitride. However that material is harder to etch selectively with the same feature aspect ratios as silicon dioxide vs Si. Also you can contaminate your factories with some materials. So these workarounds to make die shrinks more feasible all have their drawbacks. We currently see that in the 130 to 90 nm transition, problems are still hampering high clock speeds. This will be even more so with the transition from 90 nm to 60 nm.

So I hope that a G5 Peg3 will be out soon with MOS 1.5 with a complete C++ compliant gcc version

Note that P4’s integer units are double pumped i.e. 2X the rated clock speed e.g. P4@ 3.2 Ghz has integer units @6.4 Ghz.

Reference
http://chip-architect.com/news/2001_10_07_AMDs_long_term_options.html

Quote:


So what?
Everyone knows this since years.

But did you know that the engine of my motorbike can do over 10000 revolutions per minute?
This is many times more revolutions than the engine of ocean ship can do!

Revolutions != power!
Otherwise the navi would bould motorcycle engines into their ships.

Everyone knows that Clockrate != processing-power.

The Pentium IV was an experiment to build a ship tuned for very high clockrates.
Because many people thing high clock rates equal high performance those chips sell good.
Mostly all CPUs have more processing power clock per clock than the Pentium IV.
Even Intel admitted that the race for higclockrates is a deadend.
Intel will focus again on chips like the Pentium M which isn't double pumped and doesn't
reach the high clockrates of the Pentium IV but still outperforms much higher clocked P IVs.

We should not wait for Pegasos with G5,G6, ..or G99
The current Pegasos II with G4 is already an excellent computer.

The new 7447 gives excellent perfomance and together with the high speed and low footprint of MOS
the Pegasos II is a superp machine. And Genesi could easily produce today with no changes a Pegasos II with 1.5 Ghz G4. A 1.5 G4 with MOS will rock.

On my opinion the very best thing for Genesi is on focusing to produce Pegasos II with G4.
Freescale (ex Motorola) does not sleep. While we wait for MOS 1.5 - freescale is improving the G4.
Soon there will be faster G4 available. The G4 still has room for improvements. Give freescale
a few month time, let them produce G4 in 90nm instead of 130nm and you will get G4 with
2.0 Ghz clockrate which might even run passivly. Those G4 will make very nice CPUs for current Pegasos.


Cheers
Gunnar

@Hammer:
Did you know that the IA32 architecture has 12 general purpose registers whereas the PPC32 has 32?
Did you know that 3/4th of the instructions in an average IA32 application accesses the memory due to the low number of registers? (Which is why you need really fast memory on a PC)
Did you know that SSE specifies 8 128-bit registers whereas AltiVec has 32?
Did you know that the IA32 was designed in the 1970's and that all processors based on it (including the P4) are backwards compatible with the first IA32 design?
Did you know the PowerPC was designed in the late 1980's, early 1990's?

This list can be made very long. Intel is pushing the clockrate further and further each year and is not much concerned with the relatively outdated CPU design. The reason for this is that most people don't know anything about processor design, they just assume that clockrate is everything, and therefore, clockrate sells.
This does not apply to the IA64 which is based on a much more modern design (VLIW). This CPU is not target at the desktop market though.

There are some interesting articles on the PPC970
here and here.
One interesting quote from one of those two articles is the following...
Quote:
And that is for a 130 nm version, the 90 nm would be even better. So a downclocked G5 would not be such a bad idea.


[ Edited by azalin on 2004/7/25 14:06 ]

@dholm

My post was about the real clock speed within Pentium IV in relation to integer units. In another words Netburst architectures (“Rapid Execution Engine”™) needs those tricks to remain competitive with wide approach pipelined processors. Such tricks has yet to be applied to other processors.

Quote:
IA32 ISA only has 8 GPRs, 8 X87* and 8 XMM. While X86-64 has 16 GPRs, 8 X87* and 16 XMM.

*With AMD arch
_ K7-XP recycles X87 registers for 3DNow (SIMD). While "3DNow Pro" is just relabel of SSE (which uses XMM regs). A total of 16 SIMD registers (8 X87/3Dnow/MMX + 8 XMM).
_K8's a total of 24 SIMD registers (8 X87/3Dnow/MMX + 16 XMM).

On micro-architecture level, AMD’s K7 and K8 also has 8 additional registers for microcode engine. This is hidden from the programmer and exclusively use by micro-code engine.

More registers are in register wheel for micro-architecture level improvements (i.e. reducing load/store memory access for storing register data closer to the processor).

Quote:
Refer to K7 Athlon XP-M(with Bartons core) and VIA KT133A (MSI-6330) reasonable performance levels.

Requirements for massive bandwidth is for Pentium IV(Netburst).

Quote:
Note that modern X86 processors (since P6 and K5) doesn't directly execute X86-32 instructions i.e. they convert them into fix length RISC like instructions i.e. taking one of basic concepts of RISC. Such design doesn't exist in pre-P6/K5 X86 architecture.

Please review RISC concepts and Post-RISC architectures in X86.

Quote:
Note that same argument can be made from VILW view point against Pure-RISC, FRISC and Post-RISC.

Quote:
That’s a stupid statement since you haven’t factored in ISA architecture and micro-architecture.

The 8086 executes instructions at variable length while P4 executes fix length instructions (one of the basic RISC concepts)(after decoding) and register wheel and extra micro-coding registers increases on-chip registers (one of the basic RISC concepts). The 8086 micro-architecture is long dead.

Note that; the custodian of X86 ISA is now with AMD’s hands since Intel has practically being a follower in X86’s next evolution.

Please try again…

[ Edited by Hammer on 2004/7/25 14:26 ]

[ Edited by Hammer on 2004/7/25 14:29 ]

Quote:
The purpose of my post was for highlighting the true high clock speeds in P4 (netburst) architecture. This is due to Pentium IV’s being narrow approach. This trick was use to compete with wide approach processors.

Quote:
It’s IPC x clock speed. Pentium IV is extremely bias towards clock speed in expense of wide approach (related to IPC).

Quote:
This is due to cooling/power issues and post-Prescott successor’s dead end.
Using their +6Ghz fabrication processes now is eating their future reserve capabilities.

@dholm
Read this article.
Note that the story is not about the P4 but of the architecture of P3 and below (so not about netburst).
Quote:
Quote:
The PPC uses register renaming as well by the way. The pentium M is based on the above described core.

Quote:
Note that AMD's Athlon converts X87 FPU stack model into absolute FPU model i.e. AMD advances Intel’s post-RISC X86 designs to cover X87's weakness.

[ Edited by Hammer on 2004/7/25 14:21 ]

Quote:
Depends on applications; refer to
http://www.anandtech.com/mb/showdoc.aspx?i=2128
(AMD's Socket 939 vs Intel's Socket 775)

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2129
(Dothan investigated)

[ Edited by Hammer on 2004/7/25 14:37 ]

Those are some interesting links, thank you. By the way one of the reasons why I like the PPC970 (dubbed G5 by Apple) so much is the following:
Quote:
Quote:
Quote:

Hi Hammer,

Thanks for explaining your post.
I think I misunderstood it.


It looks like we all agree that the PPC architecture is not too bad.


Cheers
Gunnar

[ Edited by BigGun on 2004/7/25 22:33 ]

I don’t recall applying any negative remarks on PPC MPUs. Available motherboards for purchase are another issue altogether.

Quote:

But...
They can only work at that speed for 16 bit values, they did develop 32 bit versions at that speed but I don't think they've ever put them into production.

In any case I think they were planning to remove the double clocked stuff.

I wish they woould hurry up and meake an SMT version of this 970 for consumers




edit
---------------------------------------------------------------------------------------

well , I guess it pays to read sometimes......grrr

http://www.theregister.co.uk/2004/07/26/ibm_ppc970mp/

(seems motorola/freescale is doing it also)










----------------------------------
The champ takes 6 in the Tour de Lance

[ Edited by DethKnight on 2004/7/27 0:32 ]

[ Edited by DethKnight on 2004/7/27 0:33 ]

There is a new article on Ars about netburst (P4).
http://arstechnica.com/cpu/004/pentium-2/pentium-2-1.html

Quote:

From one of the articles about the PPC970 it seems the vector unit was "tacked on" so it is not as efficient as the one of the G4 per clock - however if your compiler schedules the instructions better it is as efficient, and because of the higher clock speeds this will speed it up.

What we really need in the future is a PPC core with an XDR ram interface ( http://www.rambus.com/products/xdr/arch_overview.cfm ) and added vector units. An order of magnitude increase in RAM speed would mean processors will not be stalled as much because they are waiting on cache fetches.