>> Do you think the Cortex-A57 will be introduced with a clock rate below 2.1 GHz?

> whether it will make it to (or above) 2.1 is questionable.

No Dhrystone, but more real-world comparison by ARM Ltd. between Cortex-A57 and Cortex-A15:

http://www.arm.com/images/A57performance_webpage.png

Yep, pretty vague.

But it looks like 64 bit will do OK.
The jump is not that surprising considering the difference between the A9 and the A15.
And the A9 is no slouch.

Update:

> Denver in 2015:
> https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=8783&forum=3&start=54

...or even in 2014 with Tegra K1 ("Tegra 5", "Logan") still?

"Tegra K1 is offered in two pin-to-pin compatible versions. [...] The second version uses a custom, NVIDIA-designed 64-bit dual Super Core CPU. This CPU (codenamed "Denver") delivers very high single-thread and multi-thread performance. It is based on the ARMv8 architecture [...]. [...] the 64-bit version is expected in devices in the second half of the year."
http://nvidianews.nvidia.com/Releases/NVIDIA-Unveils-Tegra-K1-a-192-Core-Super-Chip-That-Brings-DNA-of-World-s-Fastest-GPU-to-Mobile-a8a.aspx

"The Denver cores (and the rest of the SoC) are fabricated on TSMC’s 28nm HPM process and be clocked at up to 2.5GHz."
http://www.extremetech.com/computing/174023-tegra-k1-64-bit-denver-core-analysis-are-nvidias-x86-efforts-hidden-within

Well Andreas,
It promises to be an interesting year.
Curiously enough, some PPCs will still hold an edge over even the latest ARM designs (in particular in the number of threads possible).
But with these two jumps, 64 bit and higher clock speeds, the ARM ISA is finally starting to be really competitive with other mainstream ISAs.

Quote:

Dear THM, its good to hear overall good news that PPC isn`t that as dudo, as many have claimed and laughed. Its not faster player too, but let it become better.

Surely, that doesn`t mean ANYTHING automatically until we support some CPU and MOS needs to add AMCC now and maybe Freescale soon (so X2000 should be a viable target too ... ).

I really like ARMs but was bitterly dissapointed that dual core Prestigio tablet was unable to drive Linux and Android 4.x is ... just not for me.

ARM is the future, and M$ supporting another ISA after WinNT PPC/MIPS is a clear sign of change. Once Office goes Linux, M$ will be more widespread.

Only good news is that Windows 8.x is a complete disaster - a mobile phone OS offered to desktops. That is shoot in a foot at least for I.

AS of MOS supporting AMCC, even PWREfficient, dual core G5 and Freescale while doing the ARM transition would be my suggestion. And not because I am ex-OS4 user, but because that strenghtens MOS. OK?

Quote:

He is actually correct on this.
Strengthening our current system would have advantages.
I for one, am tired of the 'hobbyist OS" label.
I can already do most of my work from a MorphOS machine.
An alternative box could use the unused cores and memory that we already have at our disposal.

So it begins.

4 to 8 A57 cores >= 2GHz
8 x SATA3
2 x PCIe 3 x4 slots (or 1 x x8)
Up to 128GB DDR3/4 RAM
Micro ATX

Except for the limited expansion, that is nice.

Update:

> Freescale going Cortex-A53 for i.MX (and Cortex-A57 for QorIQ):
> http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1789227
> Maybe they'll simply skip Cortex-A15 for i.MX?

Indeed they will (and also Cortex-A12 for that matter). Next after current i.MX6 with Cortex-A9 will be i.MX7 with Cortex-A7 and then i.MX8 with Cortex-A53:

http://www.freescale.com/files/training/doc/dwf/DWF13_APF_CON_T0838.pdf (pages 3 to 5)

Now I get a little bit confused....ARM is relasing planning Cortex-A17 (over A12) ...


....ok..A12 has no big.LITTLE...

[ Edited by scrAb_ 11.02.2014 - 13:06 ]

Update:

> New list of DMIPS per MHz and core figures (added Cortex-A12 and specified
> different Krait types)

Figures for Cortex-A12 and Cortex-A15 substantiated and figures for Cortex-A17 added (all according to AnandTech):

ARM Cortex-A7: 1.9
ARM Cortex-A8: 2.0
Qualcomm Scorpion: 2.1
ARM Cortex-A53: 2.3
Marvell Sheeva PJ4: 2.4
ARM Cortex-A9: 2.5
Marvell Sheeva PJ4B: 2.6
Qualcomm Krait 200: 3.1...3.3 (depending on source)
Qualcomm Krait: 3.3
Qualcomm Krait 300: 3.4
ARM Cortex-A12: 3.0...3.5 (depending on source)
Qualcomm Krait 400: 3.4...3.6 (depending on source)
Qualcomm Krait 450: 3.5
Broadcom Brahma15: 3.5 (unsure whether or not this core is just ARM Cortex-A15)
Apple Swift: 3.5
ARM Cortex-A15: 3.5...4.0 (depending on source)
ARM Cortex-A17: 4.0
Applied Micro Potenza: 4.2
ARM Cortex-A57: 4.1...4.8 (depending on implementation)
ARM Cortex-A72: 4.7...5.0 (depending on implementation)

Does anybody have DMIPS figures for the Apple Cyclone or the Applied Micro X-Gene?


Edit: now also taking these into account:
http://en.wikipedia.org/wiki/Comparison_of_ARMv7-A_cores
Edit2: added Cortex-A72
http://en.wikipedia.org/wiki/Comparison_of_ARMv8-A_cores
Edit3: added X-Gene
Edit4: renamed X-Gene as Potenza

[ Edited by Andreas_Wolf 23.04.2016 - 11:07 ]

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Quote:

That figure is probably wrong and appears to have been made up. The A17 is faster than the A12 but DMIPS won't be the best benchmark to show it.

Quote:

No idea but I've seen both compared to Haswell in performance per clock.

Update:

> Core roadmap [...] shows [...] the e6501 core (adding virtualization interrupts) for 2013/2014

First product with e6501 core announced:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=B3421
http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1900438

A PPC for the 4G market?
I am confused as to the market for this component.

> A PPC for the 4G market? I am confused as to the market for this component.

We already talked about the QorIQ Qonverge there:

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=11&topic_id=8901&start=27

More reading material:

http://www.freescale.com/webapp/sps/site/overview.jsp?code=SRVCPROV
http://www.freescale.com/webapp/sps/site/overview.jsp?code=QORIQ_QONVERGE
http://www.freescale.com/files/32bit/doc/brochure/BRSMALLCELLS.pdf
http://www.freescale.com/files/32bit/doc/white_paper/QORIQQONVERGEWP.pdf
http://www.freescale.com/files/rf_if/doc/white_paper/SMCELLRFWP.pdf
http://www.freescale.com/files/industrial/doc/brochure/ENEAUPDTCSTY.pdf
http://www.freescale.com/files/training/doc/dwf/DWF13_JNK_NET_T0991.pdf

In short, the QorIQ Qonverge is a series of base station-on-chips for the wireless infrastructure service provider market.

Thanks Andrea, I remember the e6500 cored processor, and this new core is interesting.
I wonder what other purposes the DSPs could be used for.

BTW - Surprisingly good results on the A53.
I could still see this going solo.

[ Edited by Jim 18.02.2014 - 09:21 ]

> I wonder what other purposes the DSPs could be used for.

I'd say anything DSPs are suited for in general, for instance audio and video processing.

> Surprisingly good results on the A53.

You mean its Dhrystone performance per clock located between Cortex-A8 and Cortex-A9?

> I could still see this going solo.

So can others:

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=9647&start=37

>You mean its Dhrystone performance per clock located between Cortex-A8 and Cortex-A9?

Yes, exactly, I should not be so brief with my messages.

A 64bit cpu with better than A8 performance and low power draw could definitely find a market.
Imagine what a product with 8, 16, 32GBs or more of memory could do.

> 64bit cpu with better than A8 performance

As this link shows for other benchmarks than Dhrystone, the per-clock performance of Cortex-A53 is even slightly above that of Cortex-A9.

Damn, that is better than I expected.
Have you noticed that new ARM introductions tend to be more impressive than expected.
I never anticipated the large jump from A9 to A15.

> AFAIK most ARM CPU's are bi-endian. At least I think that's the case with ARMv7/Cortex

After half a decade of assumptions, speculation and guesswork here on MorphZone, I think I found the definite answer on the question of ARM's endianness using these references:

http://translatedcode.wordpress.com/2012/04/02/this-end-up/
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0203g/Chddgffb.html

The gist of it is that ARM knows one little-endian mode (on both data and code level, aka true little-endian) and two big-endian modes: BE32 and BE8. BE32 is big endianness on both data and code level (aka true big-endian), whereas BE8 is data-only big endianness.

BE32 is supported by:
- ARMv4
- ARMv5
- ARMv6

BE8 is supported by:
- ARMv6
- ARMv7
- ARMv8

Quote:

Andreas, you're the man! Good find. I almost gave up about that issue.
The beefier ARMs hence don't have the benefit of an easier to accomplish binary compability.

The Raspberry pi however is ARMv6 based....

Quote:


Don't really see the problem here (or I failed to understand the linked text).

BE8 would still allow all system-structures to be 1:1 copies of 68k/PPC ones.

All data handled by an app internally can also be BE8 without problem.

The only thing we would need is an elf-loader making sure it load code-segments as LE and data-segments as BE (which I assume would be trivial).

Same for an 68k or PPC EMU, all data is BE and so is all legacy code (which is just data for the EMU), only the snippets of ARM-code it wants executed have to loaded a LE.