Andreas my english is not good and for me is difficult to write .
>Why? I don't see where the lstopo output shows more than one SoC.
the soc if one on the topo have to be one only ... if you see the image you will see two with same id
>So you say that the Cyrus board topology is wrong because QEMU can't recreate it? Wouldn't it rather mean that there's >something wrong with QEMU if it can't recreate the topology of an existing board?
>> this has nothing to do with the board design, don't you think?
yes the cpu scheme is all ok, are the pci bridges and soc strange
>What's wrong with the L3 cache in the lstopo output?
Nothing strange there about L3 cache is ok in the topo . but it is used only for corenet and not as sdram
for be sdram have to be set up in source config of uboot ... but no one setup it. and build.
i hope now is better :P
> my fear is the e5500 true speed is ddr 200 at true 400MTs data rate.
by the way 1 GB/s to 4 gb/s max for 5040 are not DD3 1600 speed .. (stream and linux kernel report)
1 GB/s to 2 gbs max for 5020
G5 Quad is 7/8 Gb/s near 10Gb/s in Altivec
Os4 ragemem Performances of 5020 image.jpg
So you say that the Cyrus board topology is wrong because QEMU can't recreate it? Wouldn't it rather mean that there's something wrong with QEMU if it can't recreate the topology of an existing board?
nope ... the topology of the cyrrus is totally strange compared all topology in the world Informaic Tecnology.
qemu dont manage it because strange.
check and compare topos:
PowerMac G5 Quad
https://www.dropbox.com/s/8rgcvr6532fmzt5/16128954_10208172248685531_756994869_n.png?dl=0[ Edited by tlosmx 10.09.2017 - 23:12 ]