It is obvious that everything below amiga gui and graphics should be dropped.
Replacing old api with new not compatible with today's standards is dumb idea.
I still hope MOS Team will made something usefull not shit like AROS.

Quote:

Yes, yes it has. It doesn't have the nostalgia feel of using an original keyboard and looking at a crt monitor with scanlines, but for functionality and speed it easily overtook Amiga-68k. Heck, I have an Amiga 500 with Vampire v2. It is great! It cannot run Payback as well or as fast as WinUAE. Even if you had an A4000T with CSPPC and Voodoo3 3000, it would not run Payback as fast as WinUAE.

In WinUAE you can dial in any settings needed. You can literally run any software ever made for the Amiga. Real hardware is not as fortunate. Sideways and backwards compatibility was never an Amiga strong suit.

Quote:

It has a lower power draw, that's about it. Even if it did come even with my G5 2.7 one day, it would still cost literally 25x times as much as I paid for my G5 with MorphOS license.

Quote:

Better (possible) GPUs are also a thing.

At least as long as G5s are restricted to AGP.

>> I think the G5 has already been topped by the X5000 in at least
>> some aspects, even if it is still faster when Altivec is used.

> It has a lower power draw, that's about it.

https://morph.zone/modules/newbb_plus/viewtopic.php?forum=11&topic_id=11137&start=603

With a 2.7 GHz G5 instead of my 2.3 GHz G5, the index of the G5 would increase from 1.00 to 1.17. This would result in the 2.7 GHz G5 being slower than the 2.0 GHz P5020 in 33% of cases (non-SIMD integer operations).

Quote:
Of course I do know and use WinUAE from time to time. Everybody does. My point is not much about nostalgia here, it's about WinUAE slowing down a lot if you use Full Chipset Emulation and some cycle exact timings and/or MMU emulation. The config imitating my A1200/030 sometimes is actually slower than the real A1200.

But that's ok as I don't use it regularly. Software/Games which depend mostly on the CPU and/or use a RTG screen will undoubtedly get a great speed boost from WinUAE. That of course is a big plus for anybody using such software, but does not matter much for me, 'cause WinUAE can get slow in my use cases and I am too lazy to switch configs and reboot.

WinUAE isn't perfect but it covers just about anything you can do on the Amiga that you can't do elsewhere. That's what it was designed for.

Playing later Amiga games like Napalm, Payback (with caveats) Foundation or Genetic Species will run faster than any real Amiga system (won't comment on Vampire as I haven't seen it in action). And whdload works on basic 040+MMU emulation. You can play any Amiga game you like, from ADF for WHDLoad images: I don't know if there's a single one that is incompatible with WinUAE.

Playing Doom or Quake on it is iffy, but you can play doom on Windows. Same with watching video or browsing.

When phase5 decided to go the PPC route, there still was a genuine advantage in being able to mix old Amiga software with new, even doing things like using PPC-native shared libraries with old 68k apps which AROS for example could not do. Not to mention that you'd lose most of the interest if you decided to just launch a new non-backwards-compatible OS.

Today, that need is long gone. Insisting on PPC is still chasing that late 90s Amiga that doesn't even work in this day and age. There's simply no need for it any more.

[ Edited by KennyR 05.05.2019 - 21:54 ]

From developer POV ppc is interesting because it is not a pc.
commodity hardware? No problem but first AROS/MOS/ or any other amiga like solution must be not a shit compared to Windows/macOS/Linux.

Update:

> New roadmap:
> http://www.nextplatform.com/wp-content/uploads/2018/03/ibm-openpower-summit-power-roadmap.jpg
> https://images.anandtech.com/doci/13257/15348975062941567684876.jpg
> http://www.nextplatform.com/wp-content/uploads/2018/08/ibm-power-roadmap.jpg
> https://fuse.wikichip.org/wp-content/uploads/2018/09/hc30-ibm-power-roadmap.png
> https://openpowerfoundation.org/wp-content/uploads/2018/10/Myron-Slota.OPF-Summit-Oct-2018-OC-and-RM-v3.pdf (p. 12)

New roadmap:
https://www.hotchips.org/hc31/HC31_1.3_IBM.v12.pdf (pages 2-4)
http://regmedia.co.uk/2019/08/20/hotchips_ibm_5.jpg
https://images.anandtech.com/doci/14751/IMG_20190819_095752.jpg
https://fuse.wikichip.org/wp-content/uploads/2019/09/openpower-summit-roadmap2.png
http://www.itjungle.com/wp-content/uploads/2019/09/tfh093019-story01-fig01.jpg
http://www.nextplatform.com/wp-content/uploads/2019/10/ibm-omi-power-roadmap.jpg

Changes:
- POWER9 AIO postponed to 2020
- POWER10 postponed to 2021
- memory bandwidth significantly increased for POWER9 AIO and POWER10


Edit: added more roadmap links
Edit2: found an IBM document (page 4) from April 2018(!) that curiously has already some of the recent roadmap changes

[ Edited by Andreas_Wolf 15.01.2020 - 10:37 ]

OpenPOWER now even more open (mimicking RISC-V and MIPS Open):

"With IBM announcing new contributions to the open source community including the POWER Instruction Set Architecture (ISA) and key hardware reference designs at OpenPOWER Summit North America 2019, the future has never looked brighter for the POWER architecture. [...] By moving the POWER ISA under an open model [...], we’ll enable innovation in the open hardware and software space to grow at an accelerated pace. [...] In addition to open sourcing the POWER ISA, IBM is also contributing a newly developed softcore to the community. In a very short time, an IBM engineer was able to develop a softcore on the POWER ISA, and get it up and running on a Xilinx FPGA."
https://openpowerfoundation.org/the-next-step-in-the-openpower-foundation-journey/

Excellent articles on the matter, with almost no factual errors:
https://www.eejournal.com/article/ibm-gives-away-powerpc-goes-open-source/
https://www.itjungle.com/2019/08/26/what-open-sourcing-powers-isa-means-for-ibm-i-shops/
https://lwn.net/Articles/796796/
https://www.devever.net/~hl/opening-power


Edit: added links to articles
Edit2: added more links to articles

[ Edited by Andreas_Wolf 30.09.2019 - 17:42 ]

Update:

> "IBM is also contributing a newly developed softcore to the community.
> In a very short time, an IBM engineer was able to develop a softcore on
> the POWER ISA, and get it up and running on a Xilinx FPGA."

https://github.com/antonblanchard/microwatt

The PPC64LE Microwatt should be more complete than the unfinished PPC32 zCore Pippo or the finished but scalar-only PPC32 Nux at least.

"Microwatt [...] does not currently implement any floating-point or vector instructions, hypervisor mode, big-endian mode, 32-bit mode, or the HPT/SLB MMU facilities."
https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/210525.html


Edit: Chiselwatt by the same author, but written in Chisel
Edit2: added quote
Edit3: added Nux

[ Edited by Andreas_Wolf 26.03.2022 - 23:33 ]

Amiga, AmigaOS and Hyperion mentioned during OpenPOWER Summit NA 2019:

https://www.youtube.com/watch?v=bwXX4fqsPrQ

timestamps:
- 0:24
- 2:02 (only on slide)
- 25:07
- 27:36

Obviously, he means to say "A-Eon" when he mentions "Hyperion" who "manufacture PowerPC boards" and "ported AMDGPU to AmigaOS" :-)

Addendum:

> Power ISA 3.0b published in March 2017:
> https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
>
> Significant quote from Power ISA 3.0 spec: [...]
> Updated quote from Power ISA 3.0b spec: [...]
>
> Funny thing to say that Power ISA 3.0 "continues" or "focuses" the
> integration of PowerPC ISA and Book E ISA, when in fact it essentially
> *reverts* this integration by eliminating the parts that Book E ISA
> had brought into it.

At OpenPOWER Summit EU 2019, IBM director and OpenPOWER president Mendy Furmanek completely misrepresented the fate of the Book E ISA ("PowerPC Embedded") components within OpenPOWER Foundation's Power ISA 3.0+:

https://www.youtube.com/watch?v=ufBtrGJVF6g (5:40-6:40)

Not only does she unjustifiably give credit to the OpenPOWER Foundation for the integration of PowerPC ISA and Book E ISA when in fact it was Power.org that accomplished this 7 years earlier in 2006, she also fully ignores that what OpenPOWER actually did 4 years ago with the release of its Power ISA 3.0 was essentially reverting this integration by eliminating the former Book E ISA components.

> https://github.com/antonblanchard/microwatt
> [...] Chiselwatt by the same author, but written in Chisel

Interesting new project called Libre-SOC:

"we are developing a hybrid CPU-VPU-GPU in the nmigen HDL, and it is also a dual-ISA processor: RV64GC in userspace, and Power ISA in userspace and kernelspace."
http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2020-March/000001.html

Details: https://libre-soc.org/openpower/
Marketnext hackathon video: https://www.youtube.com/watch?v=Px6eakWja3Q



Edit: added video link

[ Edited by Andreas_Wolf 06.05.2020 - 16:50 ]

Update:

> Significant quote from Power ISA 3.0 spec:
> "In 2006, Freescale and IBM collaborated on the creation of the Power ISA Version
> 2.03, which represented the reunification of the architecture by combining Book E
> content with the more general purpose PowerPC Version 2.02. Power ISA Version
> 3.0 continues this integration by providing a single Book III for all Power
> implementations, and also by eliminating optional architecture categories to
> ensure increased application portability between Power processors."
>
> Updated quote from Power ISA 3.0b spec:
> "In 2006, Freescale and IBM collaborated on the creation of the Power ISA Version
> 2.03, which represented the reunification of the architecture by combining Book E
> content with the more general purpose PowerPC Version 2.02. The resulting
> Architecture included environment-specific privileged architecture optimizations
> (two Book IIIs) and optional application-specific facilities (categories) as
> extensions to a pervasive base architecture. Power ISA Version 3.0 B focuses this
> integration by choosing a single Book III and a set of widely used categories to
> become part of the base architecture for all forward-looking Power
> implementations. All other optional architecture categories have been eliminated
> to ensure increased application portability between Power processors. Legacy
> embedded applications that require the eliminated material will continue
> to use V. 2.07B."
>
> Funny thing to say that Power ISA 3.0 "continues" or "focuses" the integration of
> PowerPC ISA and Book E ISA, when in fact it essentially *reverts* this integration
> by eliminating the parts that Book E ISA had brought into it.

Slightly updated quote from brand-new Power ISA 3.1 (POWER10) spec:
"In 2006, Freescale and IBM collaborated on the creation of the Power ISA Version 2.03, which represented the reunification of the architecture by combining Book E content with the more general purpose PowerPC Version 2.02. The resulting architecture included environment-specific privileged architecture optimizations (two Book IIIs) and optional application-specific facilities (categories) as extensions to a pervasive base architecture. In support of the OpenPOWER Foundation’s standardization of server architecture, Power ISA Version 3.0 streamlined this integration by choosing a single Book III and a set of widely used categories to become part of the base architecture for all forward-looking Power implementations. All other optional architecture categories were eliminated to ensure increased application portability between Power processors. Legacy embedded applications that require the eliminated material will continue to use V. 2.07B."

I'm not sure that changing the wording from "focuses" to "streamlined" eliminates the misrepresentation of the facts.

Also interesting from the 3.1 spec:
"Power ISA Version 3.0C took the first step in reintroducing optionality into the architecture as the Power ISA moves to an “open” model governed by the OpenPOWER Foundation. Material later in the preface identifies compliancy subsets of the architecture and the optional features which they comprise. [...] Change bars have been included in the body of this document to indicate changes from the Power ISA Version 3.0C. [...] Version 3.1 of the Power ISA [...] is intended to supersede and replace version 3.0C. [...] This version was created by making miscellaneous corrections and by applying the following requests for change (RFCs) to Power ISA Version 3.0C. Change bars in this summary of changes indicate changes relative to v3.0C."

Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

Addendum:

> Interesting new project called Libre-SOC: [...]
> Details: https://libre-soc.org/openpower/

New information from the company behind Libre-SOC:

https://systemeslibres.org
https://systemeslibres.org/updates/just-incorporated/
https://systemeslibres.org/updates/code_to_tapeout/

Schedule:
- 2020 "shuttle smoketest" tapeout of 180nm (TSMC) embedded-class single-core chip, OOO, pipelined
- 2021 commercial single-core or quad-core (information are conflicting here) chip with GPU
- 2022 commercial 0.8-1.0 GHz quad-core chip with GPU (25-50 GFLOPS), 1080p25 video, VPU, DDR SDRAM controller, SERDES, UART, LPC, JTAG, GPIO, 3 watts power consumption

Sponsors:
- current: NLNet, RaptorCS
- previous: Purism

Other interesting statements:
"RaptorCS is taking a serious look at our future line up of fully POWER compliant 4-core chips."
"Libre-SOC was originally targeting RISCV, but RaptorCS expressed interest in a POWER SOC, so we pivoted to IBM’s Open POWER ISA."

I guess Raptor is considering this Power SoC to replace the current ARM/ColdFire-based ASPEED BMC, hence the requirement for LPC.

Update:

> https://github.com/antonblanchard/microwatt
[...]
> Edit: Chiselwatt by the same author, but written in Chisel

IBM has opened the A2 core:

https://github.com/openpower-cores/a2i
https://git.openpowerfoundation.org/cores/a2i

"“A2I has demonstrated it’s durability over the last decade – it’s a powerful technology with a wide range of capabilities,” said Mendy Furmanek, President, OpenPOWER Foundation and Director, POWER Open Hardware Business Development, IBM. “We’re excited to see what the open source community can do to modernize A2I with today’s open POWER ISA [...].”"
https://openpowerfoundation.org/a2i-power-processor-core-contributed-to-openpower-community-to-advance-open-hardware-collaboration/

"Modernizing" a Book III-E core into something that was called Book III-S in PowerISA <3.0? I'm not sure this is technically feasible. Why am I not surprised that Furmanek proposes this (see comment #163)?


Edit: slides and video from OpenPOWER Summit NA 2020
Edit2: added link to another repository

[ Edited by Andreas_Wolf 18.10.2022 - 13:17 ]

Update:

>> Interesting new project called Libre-SOC: [...]
>> Details: https://libre-soc.org/openpower/

> New information from the company behind Libre-SOC:
> https://systemeslibres.org
> https://systemeslibres.org/updates/just-incorporated/
> https://systemeslibres.org/updates/code_to_tapeout/

Project to be presented at XDC 2020 in September:

https://xdc2020.x.org/event/9/contributions/607/

Some questionable statements from the description:

"The core processor design [...] is to be an augmented POWER9 compliant design"

Libre-SOC surely isn't to be a POWER9-compliant design, let alone an augmented one. It is, just like POWER9, to be a PowerISAv3-compliant design.

"This [...] project [...] is also based on [...] the CDC 6600. With help from Mitch Alsup, the designer of the Motorola 68000, it has been possible to upgrade the 6600 core to multi-issue and precise exceptions with no architectural compromises."

According to that web page, Alsup is a designer of the ill-fated 88k, not of any 68k. The 68k designers are listed as:

68000: Stritter, Zolnowsky, Gunter, Leitch, Shustek, Tredennick, Crudele, McAlister, Crisp, Spak, Lee
68010: Zolnowsky, MacGregor
68020: Moyer, Mothersole, Zolnowsky, MacGregor
68030: Boney, MacGregor, Moyer, Lamb, Vegesna, Rupp
68040: Shahan
68060: Circello


Edit: slides available, fortunately without the above-mentioned claims

[ Edited by Andreas_Wolf 18.09.2020 - 14:03 ]

"This [...] project [...] is also based on [...] the CDC 6600. With help from Mitch Alsup, the designer of the Motorola 68000, it has been possible to upgrade the 6600 core to multi-issue and precise exceptions with no architectural compromises."


That statement IS peculiar.

> That statement IS peculiar.

Further web search reveals that this 68000 claim with regard to Alsup has been made by the Libre-SOC project lead for quite a while (reaching back to when the chip's ISA was still planned to be RISC-V instead of Power):

https://libre-soc.org/nlnet_2018/
https://libre-soc.org/marketnext/libresoc_story_15may2020/
https://hardware.slashdot.org/comments.pl?sid=14078694&cid=58696484
https://hardware.slashdot.org/comments.pl?sid=14078694&cid=58697004
https://hardware.slashdot.org/comments.pl?sid=14281964&cid=58866166
https://hardware.slashdot.org/comments.pl?sid=14906120&cid=59251726
https://www.phoronix.com/forums/forum/hardware/processors-memory/1064199/page4#post1064382
https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124/page5#post1104250
https://www.crowdsupply.com/libre-risc-v/m-class/updates/comments-on-recent-phoronix-articles
https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/11
https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/f202z4c/.compact
https://list.libresilicon.com/pipermail/libresilicon-developers/2019-April/000688.html
https://lists.librecores.org/pipermail/discussion/2019-April/000724.html

The claim was questioned a year ago, but the question got ignored:

https://hardware.slashdot.org/comments.pl?sid=14281964&cid=58872238

Instead, he's been repeating this claim to this day.

Reduces the veracity of his claims, doesn't it?

I wonder how much of the stuff he has said about Raptor is BS?

And if the chip is only suited to replacing a system monitoring processor, is it that good?

Quote:

That is a bit troubling, isn't it. I could see making a mistake once, but repeating it and and ignoring questions? That's not a flub, that's outright lying. To say that's a pretty big lie is an understatement.

[ Edited by redrumloa 28.07.2020 - 12:22 ]

> I wonder how much of the stuff he has said about Raptor is BS?

As far as I can tell, it's mostly true. The last quote in comment #166 does not tell the real order of events, though. In reality, the project first switched ISA from RISC-V to Power and only then was approached by Raptor. So, Raptor expressing interest was not the reason for the ISA switch, but the ISA switch was the reason for Raptor expressing interest.

> if the chip is only suited to replacing a system monitoring processor,
> is it that good?

First and foremost, this chip is about being fully open, and only then about being "good" (whatever that means in particular) :-)
The use as a board management controller for Raptor is just an initial use case for the SoC, if it happens. This doesn't mean the chip is only suited to this end. The original specs lacked some features required for a management controller. They were added to the specs at Raptor's request. The presentation description linked to in comment #168 doesn't even mention anything about management controllers or service/monitoring processors, but "tablets, smartphones, chromebooks and more".

Well, it would look better to be associated with the designers behind a successful ISA (68K), instead of one that in my opinion was a misstep by Motorola (88K).

Funny how their probable real legacy is a design that drove Motorola to IBM's door.

And why they mention the CDC 6600 is anyone's guess, since that's so old that it isn't likely that anything related to it is terribly relevant.

Edit - Except for maybe trying to co-opt history, consider the significance of the processor. Appears to be the earliest implementation of silicon transistors. And three times faster than competing IBM designs.

One thing is for certain, this guy knows his history, and where to try to catch an updraft from.

But laying claim to 68K and 6600 heritage, while your design help is coming from an 88K designer (a design that failed to scale well), its pretty deceptive.

I'd agree with Red, he appears to be outright lying.

[ Edited by Jim 28.07.2020 - 15:51 ]

> I could see making a mistake once, but repeating it and and ignoring questions?

There's always the remote possibility that he missed the question, after all he didn't post any other comment to that news item after the question was posed. Else it's probably what Jim said in the first paragraph of comment #174.