> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/

Another OpenPOWER SIG, the LibreBMC Workgroup, is apparently planning a new 32-bit big-endian Power ISA core named A2P:

presentation video and slides
presentation video and slides (alternative link)
repository


Edit: added more links

[ Edited by Andreas_Wolf 18.10.2022 - 13:12 ]

> we'll have to wait and see how this translates
> to available products in 202X+2. ;-)

Looks like the RED Semiconductor company has been established for the purpose of commercializing the Libre-SOC technology:

https://www.redsemiconductor.com

First test chip tape-out (180nm) is claimed to be a mere 5 days away:

https://www.redsemiconductor.com/team-build
https://twitter.com/lkcl/status/1400386890923130885


Edit:

"Red Semi […] have a roadmap going single-core, quad-core, 8-core, 16/64-core chiplets, 1024-core supercomputer on substrate using 16/64-core chiplets"
https://libre-soc.org/irclog/%23libre-soc.2021-08-24.log.html#t2021-08-24T15:09:55

[ Edited by Andreas_Wolf 02.09.2022 - 11:45 ]

Lets hope this thing won't turn up in BMCs only...

> Lets hope this thing won't turn up in BMCs only...

Which one? RED's Libre-SOC, ChipEleven's PythonWatt/SuperPOWER, or LibreBMC's A2P? :-)

Any of the above.

Update:

> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/
> "PowerPi" sounds interesting. Alas, no details yet.

Some small details:

"“POWER Pi” a POWER based CPU, Single Board Computer (SBC) including RPi header. Provide platform for devs, hackers and others to easily access POWER based system."
https://www.linkedin.com/pulse/revolutionaries-openpower-momentum-open-source-hardware-venkatesh-a-c-1c

Also there (7:50-8:58):
https://www.youtube.com/watch?v=s_ek-hFhxx8


Edit: added video link

[ Edited by Andreas_Wolf 18.10.2022 - 13:11 ]

> First test chip tape-out (180nm) is claimed to be a mere 5 days away

Took a little longer: https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/

The Libre-SOC test ASIC is claimed to be "implementing a fixed-point subset of the v3.0B OpenPOWER ISA", which is strange considering that compliancy subsets were introduced only with v3.0C of the ISA. There are no subsets in v3.0 or v3.0B.

Fun fact: "The Cell Library used, FlexLib, […] was developed by Staf Verhaegen of Chips4Makers […]." This happens to be MorphZone member Fats.

And of course, also this significant event doesn't come without some dubious statements from the project lead:

"Libre-SOC […] is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years."
Well, during the last 12 years, Freescale/NXP has released more than a dozen different e200-based ASIC products (not counting variants of those), the most recent one being the 16nm S32R294 released this year. Also, the entire QorIQ T family and most of the QorIQ P family are younger than 12 years. Would be interesting to know which 2009-ish non-IBM Power ISA ASIC with IBM-independent microarchitecture he's referring to here in particular, and why he doesn't accept all those later NXP/Freescale ASICs to meet his mentioned criteria.**

"they had to go through some serrioous review to get OpenPOWER out the door and into the OPF, ironically it's been ongoing for something like a decade, long before RV existed."
To contrast this with the timeline as it took place in the real world:
2010: RISC-V project started
2011: first version of RISC-V ISA released
2013: OpenPOWER Foundation founded (as OpenPOWER Consortium)
2015: RISC-V Foundation founded, Power ISA v3.0 released*,***


* Edit1: more of this nonsense

** Edit2: He tried again and failed once more:
"our […] test ASIC […] is […] the world's first Power ISA 3.0 [ASIC] outside of IBM to reach Silicon in over 12 years."
How can there have been a Power ISA v3.0 ASIC over 12 years ago when Power ISA v3.0 was published only 6 years ago? Which ASIC is he referring to with this statement? Unless I missed something, Libre-SOC is the first Power ISA v3.0+ ASIC outside of IBM ever.

*** Edit3: even more of this nonsense:
"Power ISA [...] pre-dates the RISC-V instruction set by a long way. As does interestingly their intention to open up the ISA, which was initiated about 10 years ago"

[ Edited by Andreas_Wolf 02.05.2023 - 23:50 ]

>> the pre-existing yet until now secret A2O
>> [...]
>> https://openpowerfoundation.org/openpower-foundation-introduces-ibm-hardware-and-software-contributions-at-openpower-summit-2020/
>> https://github.com/openpower-cores/a2o
>> https://git.openpowerfoundation.org/cores/a2o

> Not too shabby for an embedded core.

Ananth, an A2O-based SoC, in development:

https://www.youtube.com/watch?v=FIn1g1jfdVk


Edit: OpenPOWER Summit NA 2021 will have a session on this SoC.
Edit2: Session published.
Edit3: Super Computing 22 OpenPOWER ADG Workshop will have a session on this SoC.

[ Edited by Andreas_Wolf 02.11.2022 - 20:24 ]

Update:

> POWER10

Seems it will be Power10 instead of POWER10:

https://www.rpgpgm.com/2021/07/ibm-updates-power-branding.html
https://www.itjungle.com/2021/08/02/no-more-shouting-the-name-power-well-except-in-our-title-here/
https://www.ibm.com/it-infrastructure/power/power10

…which in my humble opinion is a stupid decision for the following reason:
So far, Power has been (since superseding PowerPC in 2006) the name of the instruction set architecture (ISA), while POWER has been the name of IBM's line of server CPU microarchitectures (POWER1…9, with POWER3…5 implementing PowerPC ISA and POWER5+…9 implementing Power ISA). This means that so far, the (non-)capitalization of the word can be used for distinction between ISA and microarchitecture. With Power10, this will be no more. The ISA and the IBM server CPU microarchitecture will both go by the very same name: Power. So what will be the correct answer to the question whether 440/460/470, A2, e200, e500, e5500, e6500, PA6T or any of the new (soft)cores discussed in this thread are Power? Well, it will depend on what the questioner has in mind, making room for misunderstandings. The correct answer will be 'yes' for Power [ISA], but it will be 'no' for Power [microarchitecture].

Update:

>> PowerPi Workgroup: https://openpowerfoundation.org/groups/powerpi/
>> "PowerPi" sounds interesting. Alas, no details yet.

> Some small details: [...]

Some more details on PowerPi / POWER Pi / POWERπ from OpenPOWER Summit NA 2021:

- SBC with dual-core or quad-core SoC ASIC
- slightly bigger than Raspberry Pi
- 150 USD max

https://www.youtube.com/watch?v=RCSKQoO5AEs (5:59-6:43)
https://www.youtube.com/watch?v=58ZmyKuB-04 (15:49-17:50)

Nice! Thanks for your constant updates on this topic @Andreas_Wolf!

Update:

> Power ISA 3.1 (POWER10) spec

Power ISA 3.1B spec released as of September 2021. Seems that this is what Power10 actually implements.

https://files.openpower.foundation/s/dAYSdGzTfW4j2r2/download/OPF_PowerISA_v3.1B.pdf
https://wiki.raptorcs.com/w/images/d/d3/OPF_PowerISA_v3.1B.pdf
https://openpowerfoundation.org/specifications/isa/


Edit: added another URL

[ Edited by Andreas_Wolf 23.02.2023 - 19:01 ]

Update:

> Looks like the RED Semiconductor company has been established
> for the purpose of commercializing the Libre-SOC technology:
> https://www.redsemiconductor.com

"The processor [...] will be able to run x86 code in native mode thanks to emulation capabilities, according to David Calderwood, chairman of the company. [...] The x86 emulation capability may be the result of technology that came to IBM when it acquired Transitive Corp. in 2008."
https://www.eenewsanalog.com/en/uk-startup-is-raising-funds-for-open-power-processor/

Wait, "native mode" or "emulation", which one is it? If the former, I'm not sure the actual developers of the CPU are aware of this capability announced by the company chairman. The article author's reference to long-abandoned, 32-bit-only QuickTransit/PowerVM Lx86, which is probably pulled out of thin air, implies a purely software-based emulation, in which case I'm not sure what this would have to do with the actual CPU design. Furthermore, I doubt that IBM would grant free use of this technology.


Edit: RED Semiconductor is now OpenPOWER Foundation member.
Edit2: https://redsemiconductor.com/red-semiconductor-joined-the-openpower-foundation/

[ Edited by Andreas_Wolf 02.10.2022 - 02:01 ]

binutils got LibreSOC support recently (klick). And it looks like it got Altivec + VSX support too (klick).

> it looks like it got Altivec + VSX support

There's no way on earth that Libre-SOC implements VSX or VMX/AltiVec, or ever will (see also comment #202). The Libre-SOC development lead absolutely despises the SIMD concept, as opposed to true vector processing.

"Libre-SOC will be compliant with the Scalar Floating-Point Subset (SFFS) i.e. is not implementing VMX/VSX […]. Prior to the formation of the Compliancy Levels first introduced in v3.0C and v3.1 the progressive historic development of the Scalar parts of the Power ISA assumed that VSX would always be there to complement it. However With VMX/VSX not available in the newly-introduced SFFS Compliancy Level, the existing non-VSX conversion/data-movement instructions require a Vector of load/store instructions (slow and expensive) to transfer data between the FPRs and the GPRs. For a modern 3D GPU this kills any possibility of a competitive edge. Also, because SimpleV needs efficient scalar instructions in order to generate efficient vector instructions, adding new instructions for data-transfer/conversion between FPRs and GPRs multiplies the savings. […] (The existing Scalar instructions being FP-FP only is based on an assumption that VSX will be implemented, and VSX is not part of the SFFS Compliancy Level. An earlier version of the Power ISA used to have similar FPR<->GPR instructions to these: they were deprecated due to this incorrect assumption that VSX would always be present)."
https://libre-soc.org/openpower/sv/int_fp_mv/

"Scalar bitmanipulation is justifiable for the exact same reasons the extensions are justifiable for other ISAs. The additional justification for their inclusion where some instructions are already (sort-of) present in VSX is that VSX is not mandatory, and the complexity of implementation of VSX is too high a price to pay at the Embedded SFFS Compliancy Level."
https://libre-soc.org/openpower/sv/vector_isa_comparison/

"Vectorisation of the VSX Packed SIMD system makes no sense whatsoever, the sole exceptions potentially being any operations with 128-bit operands […]. SV effectively replaces the majority of VSX, requiring far less instructions, and provides, at the very minimum, predication (which VSX was designed without)."
https://libre-soc.org/openpower/sv/svp64/appendix/

"When combined with SV, scalar variants of bitmanip operations found in VSX are added so that the Packed SIMD aspects of VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios."
https://libre-soc.org/openpower/sv/bitmanip/

"Whilst SVP64 is only 5 instructions the heavy focus on VSX for the past 12 years has left the SFFS Level anaemic and out-of-date compared to ARM and x86. This is very much a blessing, as the Scalar ISA has remained clean, making it highly suited to RISC-paradigm Scalable Vector Prefixing. Approximately 100 additional (optional) Scalar Instructions are up for proposal to bring SFFS up-to-date. None of them require or depend on PackedSIMD VSX (or VMX)."
https://libre-soc.org/openpower/sv/

Quote:
Sounds reasonable. But if you are correct the binutils definition for LibreSOC
"libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64)
must stand for something else?

> if you are correct the binutils definition for LibreSOC
> "libresoc", ([...] PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX [...])
> must stand for something else?

According to the project lead on IRC, the current binutils definition for "libresoc" is simply wrong:

"i suspect those flags will have to be reduced to:
PPC_OPCODE_ISEL (if that is for the isel instruction)
PPC_OPCODE_POWER9
PPC_OPCODE_SVP64
and that's probably it"
https://libre-soc.org/irclog/%23libre-soc.2022-08-12.log.html#t2022-08-12T04:50:46

> dubious statements from the project lead [...]

Seems he now passes as a "Dr." and IBM employee ;-)

Update:

> Some more details on PowerPi / POWER Pi / POWERπ [...]

As reported by MorphZone member Peter "czp" Czanik from EuroBSDCon 2022:

"Toshaan Bharvani, who participates in the work of the OpenPower Foundation, [...] talked a few words about the upcoming Power SBC arriving hopefully mid-next year."
https://peter.czanik.hu/posts/eurobsdcon2022/

Thanks for your constant updates on this matter!

However not much news apart from your cited statement. A bit of secrecy for this OpenPower hardware..

> Thanks for your constant updates on this matter!

You're welcome.

> However not much news apart from your cited statement.

As soon as the recording of the talk is online, I'll report here in case it had more newsworthy information on the PowerPi / POWER Pi / POWERπ project.

> A bit of secrecy for this OpenPower hardware.. ;-)

Yes, unfortunately, the PowerPi SIG operates in complete confidentiality.

Update:

> Looks like the RED Semiconductor company has been established
> for the purpose of commercializing the Libre-SOC technology:
> https://www.redsemiconductor.com

Several press releases from RED Semiconductor:

"Augmenting the OpenPOWER ISA first developed by IBM, RED Semiconductor is using the draft SVP64 implementation of Vector+1 to design a family of new microprocessors to be marketed as their Vantage family, of which the first device a 2-core will be the Vantage-Luna."
https://redsemiconductor.com/libre-soc-red-semiconductor-announce-partnership/ (January 3, 2022)

"Extending the POWER ISA first developed by IBM, RED Semiconductor is using the Libre-SOC Draft SVP64 implementation of Vector+1 to design its ‘Vantage’ family of new microprocessors which will be marketed globally for high performance computing applications. "
https://redsemiconductor.com/red-semiconductor-joined-the-openpower-foundation/ (September 30, 2022)

"RED Semiconductor is working with industry partners to accelerate the implementation of a 1-core ‘Vantage’ cipher-accelerator microprocessor chipset [...]. Planned for first-customer shipments in early 2024, the ‘Vantage1’ chip will be targeted at data security and privacy applications [...]."
https://redsemiconductor.com/wp-content/uploads/2022/11/red-semiconductor-chacha20-cipher-performance-1.pdf (page 4; November 10, 2022)

And from the homepage:
"Supporting native Power ISA and translated x86 and ARM instructions, SVP64 will enable developers to break free from the constraints of traditional processing platforms, with a rapid conversion to SVP64 hardware and code architecture. [...] Advanced microprocessor chip-set optimized for OS-based compute-intensive applications: - Initial 2 and 8 core variants will scale to 1k+ cores"

[ Edited by Andreas_Wolf 15.11.2022 - 10:31 ]

Update:

>> A bit of secrecy for this OpenPower hardware.. ;-)

> Yes, unfortunately, the PowerPi SIG operates in complete confidentiality.

Statement on PowerPi by the Libre-SOC project lead and Technical Director of RED Semiconductor:

"Toshaan Bharvani started the PowerPI initiative, but it was soon taken over by naive people believing that you can get a 5 watt system to do 4-core 3 ghz 7 nm with 128-bit-wide DDR3/4/5 memory and multiple lanes of PCIe and multiple lanes of OpenCAPI in under a budget of USD 10 million, when 7nm Mask Charges are $10 million on their own."
https://lists.debian.org/debian-powerpc/2023/03/msg00014.html

I'm not really sure what to make of this.

> of course, also this significant event doesn't come without
> some dubious statements from the project lead:
> "Libre-SOC […] is the first wholly-independent Power ISA ASIC
> outside of IBM to go Silicon in 12 years." […]
> He tried again and failed once more:
> "our […] test ASIC […] is […] the world's first Power ISA 3.0 [ASIC]
> outside of IBM to reach Silicon in over 12 years."

Seems that whenever he has not the slightest clue when it was that something happened or became available, he claims it was (over) 12 years ago:

"what has been developed […] is the biggest upgrade to the Power ISA since Motorola's VLE Book of over 12 years ago"
https://lists.debian.org/debian-powerpc/2023/04/msg00008.html

Book VLE was officially added to the Power ISA with v2.03 in 2006, so 17 years ago (and then completely deleted from it with ISA v3.0 in 2015). The VLE instruction set itself (as well as processors implementing it) was even available from several years earlier than that, as extension to Book E.

An RFC with the full list of the LibreSoC scalar instruction set (klick), waiting for comments before external review of the OpenPower ISA working group.