> What was not clear to me is the huge difference in processor
> instruction count needed to implement an ISA v3.1 CPU. Nice
> that you can get away with just about ~200 instructions.

As outlined in comment #186, implementing a Power ISA core with ~200 instructions (SFFS, which is LCS minus SIMD/64-bit/LE and some more) or even much less (SFS, which is SFFS minus FP) is also possible and has actually been done with Power ISA v2 (see the e200z0 core as extreme example), except that it was called 'category' back then instead of 'compliancy subset' it's called now.
IBM and the OpenPOWER Foundation proudly (see comment #165) and completely removed optionality in Power ISA v3.0 (2015) for application portability reasons, requiring compliant cores to implement the full instruction set, thus making any less-than-server CPUs virtually impossible to implement. Unsurprisingly, to date there has been no other Power ISA v3.0/3.0B implementation than IBM's own POWER9 (btw, despite what's claimed on Wikipedia, Microwatt/Chiselwatt lack VSX/VMX, so cannot be v3.0/3.0B-compliant). And with the release of v3.0C (2020), IBM and the OpenPOWER Foundation acted as if they added something new and never before seen to the Power ISA. In reality, with the introduction of the compliancy subsets they just corrected their severe mistake of deprecating ISA v2's quite successful category concept.
Overall, and as current developments like Libre-SOC are testimony of, it can only be good for the Power ecosystem that IBM and the OpenPOWER Foundation came to their senses and brought back the possibility to create smaller/embedded yet modern (i.e. ISA v3) Power cores without forcing to implement a ~1000 instructions behemoth, as well as allowed royalty-free use of the ISA as of v3.0C.

> if it's true we will get ~1500 EUR Power10 boards early next year

As I understand, that's meant to be complete systems, not just boards. But early next year? When was that said?