Addendum:

> Interesting new project called Libre-SOC: [...]
> Details: https://libre-soc.org/openpower/

New information from the company behind Libre-SOC:

https://systemeslibres.org
https://systemeslibres.org/updates/just-incorporated/
https://systemeslibres.org/updates/code_to_tapeout/

Schedule:
- 2020 "shuttle smoketest" tapeout of 180nm (TSMC) embedded-class single-core chip, OOO, pipelined
- 2021 commercial single-core or quad-core (information are conflicting here) chip with GPU
- 2022 commercial 0.8-1.0 GHz quad-core chip with GPU (25-50 GFLOPS), 1080p25 video, VPU, DDR SDRAM controller, SERDES, UART, LPC, JTAG, GPIO, 3 watts power consumption

Sponsors:
- current: NLNet, RaptorCS
- previous: Purism

Other interesting statements:
"RaptorCS is taking a serious look at our future line up of fully POWER compliant 4-core chips."
"Libre-SOC was originally targeting RISCV, but RaptorCS expressed interest in a POWER SOC, so we pivoted to IBM’s Open POWER ISA."

I guess Raptor is considering this Power SoC to replace the current ARM/ColdFire-based ASPEED BMC, hence the requirement for LPC.