> the e6500 in T1 through T4 will be dual-threaded
First T1 chip got announced:
http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1705881 http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1743554 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=T1042 http://www.freescale.com/files/32bit/doc/fact_sheet/AMPT1042PFS.pdf http://www.freescale.com/files/32bit/doc/fact_sheet/T1FAMILYFS.pdf http://www.freescale.com/files/training/doc/dwf/DWF13_QorIQ_Portfolio_SanJose.pdf (SerDes lane and PCIe controller configs at pages 36/37 and 39) http://2014ftf.ccidnet.com/pdf/0163.pdf (SerDes lane and PCIe controller configs at pages 21-23) http://www.freescale.com/files/graphic/block_diagram/T1040_T1042_BD_IMG.jpg http://www.youtube.com/watch?v=V6V3cKlZW0o http://www.youtube.com/watch?v=hyU3VUT2Vpc
...and quite to my surprise (and opposed to what is being said by Freescale on other occassions*), it doesn't have the new e6500 cores but the older e5500 cores, thus neither threading nor AltiVec. I think it's notable that those are e5500 cores shrunk to 28 nm (like e6500), as opposed to the 45 nm e5500 cores of the P5 series. Furthermore, the T1042 has a DDR4 memory controller (T2080 and T4240/T4160 have only DDR3).
T1022 seems to be next (maybe it has a DIU like the P1022): http://www.freescale.com/files/training_pdf/FTF/2012/americas/WBNR_FTF12_NET_F0009.pdf (page 59) http://2012ftf.ccidnet.com/pdf/0009.pdf (page 52) http://www.freescale.com.cn/cstory/ftf/2012/pdf/0009.pdf (page 52)
Edit1: Added Youtube video link. Edit2: Added another PDF link. Edit3: Added T1040. Edit4: Added another PDF link. Edit5: Added another PDF link.
