> I don't know, Andreas. From that statement, I would gather that all
> floating point operations are performed by one hardware unit designed
> the execute all three of sets of instructions.

Read further: "The VSU is the combination of the Altivec execution unit and the 4 FPUs." I read it as the VSU consisting of smaller (sub-)units like for instance the AltiVec unit. But maybe I'm just reading it wrong and it means that the VSU is now what "the Altivec execution unit and the 4 FPUs" had been before, i.e. in former implementations like POWER4/5/6 or PPC970.

> Therefore, VSX isn't a superset of the VMX/Altivec instructions

Yes, that's what I concluded, regardless of VSX and AltiVec being two distinctive physical units or being both executed by just one single unit.

> While a new PPC processor might be designed to only support VSX,
> it seems unlikely that IBM would want to do that.

Yes, but it's not only IBM I'm looking at. See (last sentence):

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=7001&forum=3&post_id=74716#74716

> I don't know what you define as a superset

http://en.wikipedia.org/wiki/Subset#Definitions

> but if Altivec is equivalent to Intel MMX , then VSX can be
> see as an analog of the later SSE instruction sets.

That sounds reasonable.