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    Andreas_Wolf
    Posts: 12058 from 2003/5/22
    From: Germany
    >>> I don't know if anyone is even developing a MIPs server chip,
    >>> never mind a competitive one.

    >> the market needs a server processor which is power efficient

    > Where is it? Which current MIPS core is suited for that?

    > The current Octeon includes 1 to 48 cores of the type i6400

    The Octeon III uses its own microarchitecture (cnMIPS(64) III, which implements MIPS64r5 ISA), not any from Imagination Technologies (I6400 implements MIPS64r6 ISA).

    > they only sell them as network server processors but they could be used
    > for other types of servers

    "Could be used for" doesn't imply "suited for" or "competitive at".

    > Now that Imagination has a 64 bit p series processor [...] it is only a matter
    > of time before they make processors of with 1 to 48 cores or more of the type
    > p6600 this will be the beginning of the return of the MIPS in the server.

    You seem to have missed that in 2014 (project announced as early as 2012), Cavium switched to ARMv8-A (AArch64) ISA for the Octeon III successor named ThunderX with 8 to 48 Thunder cores:

    https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7675&start=300
    https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7675&start=566
    https://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7675&start=636

    There's no indication Cavium will develop a new MIPS core or use any of Imagination's MIPS cores, quite to the contrary:

    http://www.cavium.com/newsevents-Cavium-Unveils-OCTEON-TX.html
    http://www.cavium.com/newsevents-Cavium-Announces-ThunderX2.html

    >> Due to its single CPU core, the SoC wouldn't be popular with anything other than
    >> single-core operating systems such as Amiga-like OS. I doubt IP licensors would
    >> go without fixed licensing fee in this case.

    > Most SoC are only used by a single operating system, I do not see where the
    > difference is.

    The difference between a single-core operating system and a single (SMP-capable) operating system is that the former can only use one single core of a multicore CPU while the latter can use more than one core concurrently.

    > when everything is hardware accelerated, there is much less uses for several cores.

    You can't hardware-accelerate everything. There will always be problems that are best solved by code running on the general-purpose CPU core(s) because it's impossible to build special accelerators for every problem out there into a single chip (or on a single board, or into a single system), especially ones to be solved by desktop operating systems.

    > as a last ressort measure, which would increase the cost per unit even more
    > but allow a fee per unit from licensor (to lower the upfront cost), it is
    > always possible to include 2 or more cores in the chip and destroy the extra
    > ones before including the chips on the board for the first production run.

    Huh? Why would you do that? MorphOS already runs fine on multicore machines by simply ignoring all but one of the cores. And on modern SoCs, unused cores can be disabled so that they consume (almost) no power. There's no need to destroy anything.

    >> The chip you described (multi-GHz, GPU, hardware overlay, SATA, USB3, GbE,
    >> IP hardware offloading, Wi-Fi, Bluetooth, NOR flash, DCT/IDCT/FFT/IFFT,
    >> layer-4 protocol checksum offloading, IR decoding, GDDR3-SGRAM and RLDRAM3
    >> controllers) would be a very complex SoC. Three or less engineers developing
    >> this SoC in their spare time would need something like a decade to get it
    >> ready for the market.

    > the work they would need to do would be integration [...].

    Yes, I know. This is what I assess would take the mentioned timeframe.

    >> In conclusion, I still think you're a dreamer.

    > All worthwile projects started as a dream.

    ...with a basis in reality :-P

    > as an absolute last resort, using an existing SoC [...] and adding the missing
    > functionnality as external circuits can be workable.

    Words of reason, finally :-)

    > destroying the unnecessary sub-units

    Why destroy and not simply disable (see above)?


    Edit: added link to Cavium's Octeon TX and ThunderX2 press releases

    [ Edited by Andreas_Wolf 01.06.2016 - 19:08 ]
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