> I don't know until I see it working.

https://www.youtube.com/watch?v=OF8qRc8y6P4
https://www.youtube.com/watch?v=pCCuqpCYZsQ

> if certain legacy apps can't be made to behave within the SMP environment,
> they could be boxed onto one core.

If I understand the AROS solution correctly, everything that has run so far will run in SMP-enabled AROS as well.

> The e5500 and e6500 with their hypervisors would be very capable of
> concurrently running a multiple number of possible single core and SMP
> concurrent operations (even concurrent 32 and 64 bit environments).

I clearly favour the AROS solution of running everything within the same environment.

> did you notice NXP's docs on interfacing DDR4 with Qorlq cpus?

You mean this? QorIQ T1 series has DDR4-compatible memory controller. Is there anything special about that implementation?