>Isn't the AROS solution capable of the former for programs using the new SMP API?

I don't know until I see it working.
But been discussing the idea of a similar solution for MorphOS for awhile as well.
And if certain legacy apps can't be made to behave within the SMP environment, they could be boxed onto one core.
The e5500 and e6500 with their hypervisors would be very capable of concurrently running a multiple number of possible single core and SMP concurrent operations (even concurrent 32 and 64 bit environments).
When you get to the e6500, the possible thread count makes things really interesting.

BTW, did you notice NXP's docs on interfacing DDR4 with Qorlq cpus?