Addendum:

> Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

Still no link to the spec, but some mention of Power ISA 3.0C in slides from ICS in June 2020 (page 2):

"April 2020 – POWER ISA 3.0c [...]
- Same as POWER ISA 3.0b except for
• Compliancy Subsets
• Custom Extension Space (Sandbox)
• SMF Feature"

(further mentions on pages 3 and 6)

Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg

Update:

> Project to be presented at XDC 2020 in September:
> https://xdc2020.x.org/event/9/contributions/607/

Also at OpenPOWER Summit NA 2020 two days earlier:

https://openpowerna2020.sched.com/event/eDqa/the-libresoc-initiative-a-hybrid-cpuvpugpu-luke-leighton-libresoc

Update:

> IBM has opened the A2 core:
> https://github.com/openpower-cores/a2i
> https://git.openpowerfoundation.org/cores/a2i

New core contribution hinted at:

https://openpowerna2020.sched.com/event/eDtC/new-core-contribution

I have a hunch it will be the PPC405. After all, IBM already opened the core to researchers and academia through Power.org back in 2006.

http://web.archive.org/web/20120722083542/https://www.power.org/news/articles/405download/

Update:

> "Microwatt [...] does not currently implement any floating-point or vector instructions,
> hypervisor mode, big-endian mode, 32-bit mode, or the HPT/SLB MMU facilities."
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/210525.html

Some weeks/days ago, Microwatt got big-endian mode, 32-bit mode and an FPU:
https://github.com/antonblanchard/microwatt/pull/239
https://github.com/antonblanchard/microwatt/pull/245

Update:

>> IBM has opened the A2 core:
>> https://github.com/openpower-cores/a2i
>> https://git.openpowerfoundation.org/cores/a2i

> New core contribution hinted at:
> https://openpowerna2020.sched.com/event/eDtC/new-core-contribution
> I have a hunch it will be the PPC405.

Okay, not the 405, but the pre-existing yet until now secret A2O, which compared to the well-known in-order A2I added out-of-order execution at the cost of being reduced from SMT4 to SMT2.

https://openpowerna2020.sched.com/event/eOyb/ibm-open-sources-the-a2o-core-bill-flynn-ibm
https://static.sched.com/hosted_files/openpowerna2020/39/Bill%20Flynn.pdf
https://www.youtube.com/watch?v=2IshMgIGCR4
https://openpowerfoundation.org/openpower-foundation-introduces-ibm-hardware-and-software-contributions-at-openpower-summit-2020/
https://github.com/openpower-cores/a2o
https://git.openpowerfoundation.org/cores/a2o
https://github.com/openpower-cores/a2o/blob/master/rel/doc/A2O_UM.pdf


Edit: added link to another repository

[ Edited by Andreas_Wolf 18.10.2022 - 13:15 ]

Update:

> [Libre-SOC] at OpenPOWER Summit NA 2020 [...]:
> https://openpowerna2020.sched.com/event/eDqa/the-libresoc-initiative-a-hybrid-cpuvpugpu-luke-leighton-libresoc

Slides available: https://static.sched.com/hosted_files/openpowerna2020/3e/The%20LibreSOC%20Initiative.pdf (video)

Page 7 has a strange claim:

"Next: create a low-cost test ASIC (180nm). (first OpenPOWER ASIC since IBM’s POWER9, 10 years ago)"

POWER9 10 years ago? 2010 was POWER7. POWER9 was 2017.

Interestingly, the claim was quoted and questioned in a discussion but this was again ignored while virtually everything else in that thread was addressed. Makes one wonder.


Edit: claim repeated in November

[ Edited by Andreas_Wolf 06.12.2020 - 22:08 ]

Quote:
Not too shabby for an embedded core. And certainly more advanced than the 405 (or the 440 of the Sam460 ex), being 32bit Power ISA v.2.03 cores (roughly POWER5), where the A2O is 64bit Power ISA v.2.07 (roughly POWER8).

But apart from being ISA v.2.07 compatible it does not seem to feature a SIMD vector unit (Altivex, VSX) nor an MMU? (klick)

> the 405 (or the 440 [...]), being [...] Power ISA v.2.03 cores (roughly
> POWER5), where the A2O is [...] Power ISA v.2.07 (roughly POWER8).

I really don't get this fixation on Power ISA revisions. The PPC405 or PPC440 are nothing like the POWER5+, even if both are Power ISA v2.03. And likewise, the A2O is nothing like the POWER8, even if both are Power ISA v2.07. The option-based way the Power ISA (except v3.0/v3.0B, which gave up on optionality) spec compliancy works (v2: categories; v3.0C/v3.1: compliancy subsets) makes the ISA revision mostly irrelevant for comparison of microarchitectures/cores. To illustrate my point, see if you can find any new feature in the v2.07 A2O compared to the v2.06 A2I that was added in Power ISA v2.07.
There's one extremely relevant thing with Power ISA versions, namely the turning point that IBM created with Power ISA v3.0 in 2015 (see comments #88, #163, #165, #167), which prevents Power ISA v2 Book III-E cores from being used commercially (i.e. hard core, ASIC) under the royalty-free OpenPOWER v3.0C or v3.1 licenses. Thus, the v2.06/2.07 A2I and A2O cores cannot be used commercially under the license by 3rd parties unless those cores be upgraded to ISA v3.0C or v3.1 level, which includes, among other things, replacing the embedded supervisor instructions (from Book III-E of Power ISA v2) by non-embedded ("server") supervisor instructions (from Book III-S of Power ISA v2, or from Book III of Power ISA v3 or pre-v2.03 PowerPC ISA). This is quite an effort.
As it stands, the commercial usability of A2I/A2O in the OpenPOWER context is not really there. IBM could have contributed not just Power ISA v3.0C and v3.1 but also old Power ISA v2 revisions to the OpenPOWER Foundation for 3rd party use, but they decided not to do this and I'm sure they have their reasons for this decision. Btw, IBM can as well open-source any of its Power ISA v2 Book III-S cores, like POWER5+ to POWER8, or any of its old pre-v2.03 PowerPC cores, like 40x (the 440 being the first IBM core with Book-E extensions), 6xx, 7xx, 970, Cell PPU (probably subject to consent by Sony and Toshiba, though), POWER3 to POWER5. Anything from that list is more compliant with Power ISA v3 than A2I/A2O is, and I'm still hopeful with regard to this.

> it does not seem to feature a SIMD vector unit [...] nor an MMU?

No SIMD, but basic MMU is there.


Edit: changed wording

[ Edited by Andreas_Wolf 05.10.2023 - 19:26 ]

Quote:
So CPUs compliant to the same ISA don't understand the same instructions? Seems a bit more complicated than I thought...

> CPUs compliant to the same ISA don't understand the same instructions?

Exactly, the Power ISA revision usually tells nothing about the supported instructions of the microarchitecture/core declared compliant with the respective Power ISA revision. With each new Power ISA revision, new optional features/instructions were added (exception: Power ISA v3.0 which killed entire Book III-E and Book VLE). Every new Power core was simply declared compliant with the ISA revision that was recent at time of release, no matter if it supported the new optional instructions or not. Usually, the big IBM POWER processors were the ones that supported the new instructions and that the new ISA revision was released for in the first place (exceptions: POWER5+/POWER5++ (ISA v2.03/v2.04) didn't implement VMX/AltiVec introduced with ISA v2.03, this took until POWER6 (ISA v2.05)). This way of assigning ISA revisions to cores has been legit as new instructions have always been optional. That's why a core declared compliant with a certain ISA revision is automatically compliant with all follow-up revisions (exception again: Power ISA v3.0).
This way, the very same ISA revisions are shared by
- cores with FPU and without
- cores with MMU and without
- Book III-S cores and Book III-E cores
- Book III-E cores with SPE and Book III-E cores without
- cores with VLE and cores without
- VLE cores with Book I-III instructions and VLE cores without
- cores with SIMD and cores without
- SIMD cores with VSX and SIMD cores without
- cores with AltiVec/VMX in both endians and cores with AltiVec/VMX only in big-endian
- 32 bit-only cores, 64 bit-only cores and 32/64-bit cores
- cores with decimal FP and cores without
- cores with transactional memory and cores without

These are just the most obvious instruction set differences. And to give you the most extreme example, both the e200z0 and the POWER5+ implement Power ISA v2.03, yet they do not have even one single instruction in common.

> Seems a bit more complicated than I thought

This graph is quite okay, but it has a major flaw: it implies that Power ISA v3.0 and above still contain Book III-E and Book VLE, which they do not. (As minor flaws, it falsely implies that Power ISA v3.0 and above have been released by Power.org, and it's missing Power ISA v3.0C.)

[ Edited by Andreas_Wolf 20.09.2024 - 13:41 ]

Addendum:

>> Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

> some mention of Power ISA 3.0C in slides from ICS in June 2020
> (page 2): [...] (further mentions on pages 3 and 6)
> Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg

Revised presentation from OpenPOWER Summit NA 2020:
https://www.youtube.com/watch?v=ZGvEpd4vNK0

Inexplicably, the occurences of "3.0c"/"3.0C" on pages 2/3 got replaced by "3.0", which is of course plain wrong as neither has Power ISA v3.0 from 2015 (or v3.0B from 2017) been contributed to the OpenPOWER Foundation nor does v3.0 (or v3.0B) have any compliancy subsets. Both things started only with v3.0C/3.1.
These changes to the slides must have been made deliberately. What the heck is going on there?


Edit: "V3.0C" mentioned in https://www.youtube.com/watch?v=SO8a8zcAiZc (at 13:00 and 20:04) and https://video.fosdem.org/2021/D.power/microwatt_grows_up.mp4 / https://video.fosdem.org/2021/D.power/microwatt_grows_up.webm (at 5:00 and 13:33)
(Btw, funny how Paul Mackerras in the first video at 11:45 claims that the ISA renaming in 2006 from PowerPC ISA (v2.02) to Power ISA (v2.03) by Power.org happened because Freescale allegedly had very much stopped using the ISA so that it was pretty much just about the IBM POWER line of server CPUs at that time (and in the second video at 4:18 that it happened because IBM allegedly was the only company using the ISA or making any new CPUs with it), when in fact the opposite is true, namely that the renaming represented the incorporation of the Book-E extensions (implemented by IBM PPC440/PPC460 and Freescale e200/e500 back then, which are embedded class and thus as un-POWER as possible) into the official ISA specification.)

[ Edited by Andreas_Wolf 18.02.2021 - 22:03 ]

Addendum:

> POWER9 AIO postponed to 2020

POWER9′/AIO/Axone cancelled?


Edit: https://twitter.com/RaptorCompSys/status/1330466886069473286

[ Edited by Andreas_Wolf 09.01.2021 - 00:10 ]

> the company behind Libre-SOC:
> https://systemeslibres.org

Systèmes Libres seems to be no more (or never was beside a website) and three months ago turned into ChipEleven:

https://chipeleven.com
https://soc.chipeleven.com
https://wiki.chipeleven.com
https://gitlab.com/chipeleven/soc
https://demoday.create-x.gatech.edu/company/chipeleven/
https://reformventures.com/portfolio
https://www.outlanderlabs.com/portfolio
https://www.pitchbook.com/profiles/company/458176-60
https://vimeo.com/488597617

Features acc. to sources:
- market-ready by spring 2022
- 3 watts power budget
- PythonWatt quad-core: pipelined, 8-stage, SMP, 1.5 GHz
- Mali GPU, 1080p60 video
- DDR4, PCIe, IPMI, LPC, USB2, GbE

As I understand it, PythonWatt is likely derived/forked from Libre-SOC's core (at least two ChipEleven contributors are former Libre-SOC contributors), and the ChipEleven SoC has somewhat different design goals than Libre-SOC, like dedicated vector unit (VSX?) and third-party GPU vs. hybrid CPU+VPU+GPU.

Comments from the Libre-SOC project lead:

"michael etc. do not full comprehend copyright law and took jointly-owned copyrighted material and are slapping an alternative license on it without permission [...]
a quick look shows that michael *might* have started from scratch, including on the power decoder"
https://libre-soc.org/irclog/%23libre-soc.2020-10-27.log.html#t2020-10-27T17:05:41
https://libre-soc.org/irclog/%23libre-soc.2020-10-27.log.html#t2020-10-27T17:27:35

"the founder of chipeleven betraying the trust we placed in them [...] put us behind by at least a year."
https://libre-soc.org/irclog/%23libre-soc.2021-03-29.log.html#t2021-03-29T16:59:11


Edit: added more links
Edit2: added another quote

[ Edited by Andreas_Wolf 24.08.2021 - 22:48 ]

>> he's been repeating this claim to this day.

> That is a bit troubling, isn't it.

He's been at it again:

"Mitch [...] studied the 6600 very early on, recognised its genious, and based the Motorola 68000 on it."
https://www.phoronix.com/forums/forum/hardware/graphics-cards/1207878-libre-soc-still-persevering-to-be-a-hybrid-cpu-gpu-that-s-100-open-source/page17#post1213463

:-(

(On another note, he's not afraid to tell an anecdote of someone in 1995 doing something on a 1998 computer running a factory-installed 2001 OS.)

Update:

> Schedule:
> - 2020 "shuttle smoketest" tapeout of 180nm (TSMC) embedded-class
> single-core chip, OOO, pipelined
> - 2021 commercial single-core or quad-core (information are conflicting
> here) chip with GPU
> - 2022 commercial 0.8-1.0 GHz quad-core chip with GPU (25-50 GFLOPS),
> 1080p25 video, VPU, DDR SDRAM controller, SERDES, UART, LPC,
> JTAG, GPIO, 3 watts power consumption

Most recent Libre-SOC schedule from the mission statement:
- 12/2020: "demo" of 180nm single-core dual-issue 64-bit QFP chip, saleable in the "Embedded" space
- later: 800 MHz quad-core dual-issue SoC with 4-wide FP32, hybrid CPU/GPU/VPU
- even later: addition of an ML inference core


Edit:

Even more recent schedule from the business plan:
- Q2/2021: 130nm test chip (Google/SkyWater MPW shuttle program)
- Q4/2021: 180nm QFP SoC
- Q2/2022: 28nm or 20nm quad-core SoC for BMC and SBC use; USB-C and PCIe host/device controllers, i.e. also usable as peripheral GPU
- Q2/2023: then-latest process node; targetting smartphones, netbooks, tablets, IoT and IPTV

Seems the previous schedule got delayed by some months.

[ Edited by Andreas_Wolf 28.12.2020 - 12:02 ]

Update:

> ChipEleven: https://chipeleven.com
> [...]
> Features acc. to sources:
> - market-ready by spring 2022
> - 3 watts power budget
> - PythonWatt quad-core: pipelined, 8-stage, SMP, 1.5 GHz
> - Mali GPU, 1080p60 video
> - DDR4, PCIe, IPMI, LPC, USB2, GbE

Some additions and changes according to website:
- market-ready by spring 2023 (i.e. a year delayed)
- SoC name: SuperPOWER
- single-issue, out-of-order execution core
- Mali-G77 GPU

Update:

>> Project to be presented at XDC 2020

> Also at OpenPOWER Summit NA 2020

Also at FOSDEM 2021 in February:

https://stands.fosdem.org/stands/the_libresoc_project__a_hybrid_3d_cpu_vpu_gpu/
https://www.fosdem.org/2021/schedule/event/libresocproject/
https://www.fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorisation/

Update:

> the project [...] was approached by Raptor. [...] The use as a board management
> controller for Raptor is just an initial use case for the SoC, if it happens.

Seems the delay in the Libre-SOC project has led Raptor to create Kestrel SoftBMC, their own FPGA-based BMC using Microwatt:

https://twitter.com/RaptorEng/status/1352082171952062468
https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex-boards/-/blob/master/README.md
https://www.phoronix.com/scan.php?page=news_item&px=Raptor-Kestrel

Update:

>> ChipEleven: https://chipeleven.com

> Some additions and changes according to website:
> - market-ready by spring 2023 (i.e. a year delayed)
> - SoC name: SuperPOWER
> - single-issue, out-of-order execution core
> - Mali-G77 GPU

Project presentation: https://www.youtube.com/watch?v=wO5o4MLGtxo

Update:

> Does anybody have a link to that "3.0C" spec?

Finally surfaced: https://wiki.raptorcs.com/w/images/7/70/PowerISA_public.v3.0C.pdf
https://ftp.libre-soc.org/PowerISA_public.v3.0C.pdf

Update:

> Microwatt got big-endian mode, 32-bit mode and an FPU

Microwatt will be manufactured as a 130nm ASIC in the Google/SkyWater MPW shuttle program:

https://openpowerfoundation.org/openpower-foundation-provides-microwatt-for-fabrication-on-skywater-open-pdk-shuttle/

Update:

> schedule from the business plan:
> - Q2/2021: 130nm test chip (Google/SkyWater MPW shuttle program)
> - Q4/2021: 180nm QFP SoC
> - Q2/2022: 28nm or 20nm quad-core SoC for BMC and SBC use; USB-C and
> PCIe host/device controllers, i.e. also usable as peripheral GPU
> - Q2/2023: then-latest process node; targetting smartphones, netbooks, tablets,
> IoT and IPTV

Most recent schedule update*:
- 202X: 300 MHz single-core
- 202X+2: quad-core
- 202X+4: 8-core
- 202X+6: 64-core

(* The notion that VSX is 15 years old is incorrect. VSX was first specified in Power ISA v2.06 in 2009 and first implemented in POWER7 in 2010.)


Edit: "Quad and 8 1.5+ ghz on the roadmap over the next 3 years"

[ Edited by Andreas_Wolf 20.07.2021 - 01:47 ]

Ah, finally we are getting somewhere! At least the 'quad-core as SBC' looks interesting. But we'll have to wait and see how this translates to available products in 202X+2.

@Andreas_Wolf: Thanks for your continuous updates! Looking at the schedule update you posted I gather that VMX/VSX will not be implemented (too much work?) for the time being?

> I gather that VMX/VSX will not be implemented (too much work?)
> for the time being?

Yes, correct. Their long-term plan is however to not implement VMX/VSX ever but instead somehow convince IBM and the OpenPOWER Foundation to abandon VSX in favour of Libre-SOC's non-SIMD SimpleV (or Simple-V, seems they can't decide on one spelling variant) vector augmentation.

Update:

> Project presentation:
> https://www.youtube.com/watch?v=wO5o4MLGtxo

Apparently, ChipEleven has joined the OpenPOWER Foundation:
https://openpowerfoundation.org/members/chipeleven/

Therein, it has become a member of the PowerPi Workgroup:
https://openpowerfoundation.org/groups/powerpi/

"PowerPi" sounds interesting. Alas, no details yet.


Edit: ChipEleven seems to be no longer a member of the PowerPi SIG.
Edit2: ChipEleven no longer OpenPOWER Foundation member
Edit3: ChipEleven listed as "Out of Business" as of "10-Mar-2022".
Edit4: Chip11 Github repository (last commit October 2022: "I don't plan to complete this processor, but rather, plan to do a new implementation in BlueSpec.")
Edit5: MannaChip Github repository ("the POWER3.0 compliant MannaChip processor delivers groundbreaking performance, necessitating minimal intervention on the developer's or user's part.")

[ Edited by Andreas_Wolf 22.09.2024 - 01:44 ]