Update:

> Significant quote from Power ISA 3.0 spec:
> "In 2006, Freescale and IBM collaborated on the creation of the Power ISA Version
> 2.03, which represented the reunification of the architecture by combining Book E
> content with the more general purpose PowerPC Version 2.02. Power ISA Version
> 3.0 continues this integration by providing a single Book III for all Power
> implementations, and also by eliminating optional architecture categories to
> ensure increased application portability between Power processors."
>
> Updated quote from Power ISA 3.0b spec:
> "In 2006, Freescale and IBM collaborated on the creation of the Power ISA Version
> 2.03, which represented the reunification of the architecture by combining Book E
> content with the more general purpose PowerPC Version 2.02. The resulting
> Architecture included environment-specific privileged architecture optimizations
> (two Book IIIs) and optional application-specific facilities (categories) as
> extensions to a pervasive base architecture. Power ISA Version 3.0 B focuses this
> integration by choosing a single Book III and a set of widely used categories to
> become part of the base architecture for all forward-looking Power
> implementations. All other optional architecture categories have been eliminated
> to ensure increased application portability between Power processors. Legacy
> embedded applications that require the eliminated material will continue
> to use V. 2.07B."
>
> Funny thing to say that Power ISA 3.0 "continues" or "focuses" the integration of
> PowerPC ISA and Book E ISA, when in fact it essentially *reverts* this integration
> by eliminating the parts that Book E ISA had brought into it.

Slightly updated quote from brand-new Power ISA 3.1 (POWER10) spec:
"In 2006, Freescale and IBM collaborated on the creation of the Power ISA Version 2.03, which represented the reunification of the architecture by combining Book E content with the more general purpose PowerPC Version 2.02. The resulting architecture included environment-specific privileged architecture optimizations (two Book IIIs) and optional application-specific facilities (categories) as extensions to a pervasive base architecture. In support of the OpenPOWER Foundation’s standardization of server architecture, Power ISA Version 3.0 streamlined this integration by choosing a single Book III and a set of widely used categories to become part of the base architecture for all forward-looking Power implementations. All other optional architecture categories were eliminated to ensure increased application portability between Power processors. Legacy embedded applications that require the eliminated material will continue to use V. 2.07B."

I'm not sure that changing the wording from "focuses" to "streamlined" eliminates the misrepresentation of the facts.

Also interesting from the 3.1 spec:
"Power ISA Version 3.0C took the first step in reintroducing optionality into the architecture as the Power ISA moves to an “open” model governed by the OpenPOWER Foundation. Material later in the preface identifies compliancy subsets of the architecture and the optional features which they comprise. [...] Change bars have been included in the body of this document to indicate changes from the Power ISA Version 3.0C. [...] Version 3.1 of the Power ISA [...] is intended to supersede and replace version 3.0C. [...] This version was created by making miscellaneous corrections and by applying the following requests for change (RFCs) to Power ISA Version 3.0C. Change bars in this summary of changes indicate changes relative to v3.0C."

Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

Addendum:

> Interesting new project called Libre-SOC: [...]
> Details: https://libre-soc.org/openpower/

New information from the company behind Libre-SOC:

https://systemeslibres.org
https://systemeslibres.org/updates/just-incorporated/
https://systemeslibres.org/updates/code_to_tapeout/

Schedule:
- 2020 "shuttle smoketest" tapeout of 180nm (TSMC) embedded-class single-core chip, OOO, pipelined
- 2021 commercial single-core or quad-core (information are conflicting here) chip with GPU
- 2022 commercial 0.8-1.0 GHz quad-core chip with GPU (25-50 GFLOPS), 1080p25 video, VPU, DDR SDRAM controller, SERDES, UART, LPC, JTAG, GPIO, 3 watts power consumption

Sponsors:
- current: NLNet, RaptorCS
- previous: Purism

Other interesting statements:
"RaptorCS is taking a serious look at our future line up of fully POWER compliant 4-core chips."
"Libre-SOC was originally targeting RISCV, but RaptorCS expressed interest in a POWER SOC, so we pivoted to IBM’s Open POWER ISA."

I guess Raptor is considering this Power SoC to replace the current ARM/ColdFire-based ASPEED BMC, hence the requirement for LPC.

Update:

> https://github.com/antonblanchard/microwatt
[...]
> Edit: Chiselwatt by the same author, but written in Chisel

IBM has opened the A2 core:

https://github.com/openpower-cores/a2i
https://git.openpowerfoundation.org/cores/a2i

"“A2I has demonstrated it’s durability over the last decade – it’s a powerful technology with a wide range of capabilities,” said Mendy Furmanek, President, OpenPOWER Foundation and Director, POWER Open Hardware Business Development, IBM. “We’re excited to see what the open source community can do to modernize A2I with today’s open POWER ISA [...].”"
https://openpowerfoundation.org/a2i-power-processor-core-contributed-to-openpower-community-to-advance-open-hardware-collaboration/

"Modernizing" a Book III-E core into something that was called Book III-S in PowerISA <3.0? I'm not sure this is technically feasible. Why am I not surprised that Furmanek proposes this (see comment #163)?


Edit: slides and video from OpenPOWER Summit NA 2020
Edit2: added link to another repository

[ Edited by Andreas_Wolf 18.10.2022 - 13:17 ]

Update:

>> Interesting new project called Libre-SOC: [...]
>> Details: https://libre-soc.org/openpower/

> New information from the company behind Libre-SOC:
> https://systemeslibres.org
> https://systemeslibres.org/updates/just-incorporated/
> https://systemeslibres.org/updates/code_to_tapeout/

Project to be presented at XDC 2020 in September:

https://xdc2020.x.org/event/9/contributions/607/

Some questionable statements from the description:

"The core processor design [...] is to be an augmented POWER9 compliant design"

Libre-SOC surely isn't to be a POWER9-compliant design, let alone an augmented one. It is, just like POWER9, to be a PowerISAv3-compliant design.

"This [...] project [...] is also based on [...] the CDC 6600. With help from Mitch Alsup, the designer of the Motorola 68000, it has been possible to upgrade the 6600 core to multi-issue and precise exceptions with no architectural compromises."

According to that web page, Alsup is a designer of the ill-fated 88k, not of any 68k. The 68k designers are listed as:

68000: Stritter, Zolnowsky, Gunter, Leitch, Shustek, Tredennick, Crudele, McAlister, Crisp, Spak, Lee
68010: Zolnowsky, MacGregor
68020: Moyer, Mothersole, Zolnowsky, MacGregor
68030: Boney, MacGregor, Moyer, Lamb, Vegesna, Rupp
68040: Shahan
68060: Circello


Edit: slides available, fortunately without the above-mentioned claims

[ Edited by Andreas_Wolf 18.09.2020 - 14:03 ]

"This [...] project [...] is also based on [...] the CDC 6600. With help from Mitch Alsup, the designer of the Motorola 68000, it has been possible to upgrade the 6600 core to multi-issue and precise exceptions with no architectural compromises."


That statement IS peculiar.

> That statement IS peculiar.

Further web search reveals that this 68000 claim with regard to Alsup has been made by the Libre-SOC project lead for quite a while (reaching back to when the chip's ISA was still planned to be RISC-V instead of Power):

https://libre-soc.org/nlnet_2018/
https://libre-soc.org/marketnext/libresoc_story_15may2020/
https://hardware.slashdot.org/comments.pl?sid=14078694&cid=58696484
https://hardware.slashdot.org/comments.pl?sid=14078694&cid=58697004
https://hardware.slashdot.org/comments.pl?sid=14281964&cid=58866166
https://hardware.slashdot.org/comments.pl?sid=14906120&cid=59251726
https://www.phoronix.com/forums/forum/hardware/processors-memory/1064199/page4#post1064382
https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124/page5#post1104250
https://www.crowdsupply.com/libre-risc-v/m-class/updates/comments-on-recent-phoronix-articles
https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/11
https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/f202z4c/.compact
https://list.libresilicon.com/pipermail/libresilicon-developers/2019-April/000688.html
https://lists.librecores.org/pipermail/discussion/2019-April/000724.html

The claim was questioned a year ago, but the question got ignored:

https://hardware.slashdot.org/comments.pl?sid=14281964&cid=58872238

Instead, he's been repeating this claim to this day.

Reduces the veracity of his claims, doesn't it?

I wonder how much of the stuff he has said about Raptor is BS?

And if the chip is only suited to replacing a system monitoring processor, is it that good?

Quote:

That is a bit troubling, isn't it. I could see making a mistake once, but repeating it and and ignoring questions? That's not a flub, that's outright lying. To say that's a pretty big lie is an understatement.

[ Edited by redrumloa 28.07.2020 - 12:22 ]

> I wonder how much of the stuff he has said about Raptor is BS?

As far as I can tell, it's mostly true. The last quote in comment #166 does not tell the real order of events, though. In reality, the project first switched ISA from RISC-V to Power and only then was approached by Raptor. So, Raptor expressing interest was not the reason for the ISA switch, but the ISA switch was the reason for Raptor expressing interest.

> if the chip is only suited to replacing a system monitoring processor,
> is it that good?

First and foremost, this chip is about being fully open, and only then about being "good" (whatever that means in particular) :-)
The use as a board management controller for Raptor is just an initial use case for the SoC, if it happens. This doesn't mean the chip is only suited to this end. The original specs lacked some features required for a management controller. They were added to the specs at Raptor's request. The presentation description linked to in comment #168 doesn't even mention anything about management controllers or service/monitoring processors, but "tablets, smartphones, chromebooks and more".

Well, it would look better to be associated with the designers behind a successful ISA (68K), instead of one that in my opinion was a misstep by Motorola (88K).

Funny how their probable real legacy is a design that drove Motorola to IBM's door.

And why they mention the CDC 6600 is anyone's guess, since that's so old that it isn't likely that anything related to it is terribly relevant.

Edit - Except for maybe trying to co-opt history, consider the significance of the processor. Appears to be the earliest implementation of silicon transistors. And three times faster than competing IBM designs.

One thing is for certain, this guy knows his history, and where to try to catch an updraft from.

But laying claim to 68K and 6600 heritage, while your design help is coming from an 88K designer (a design that failed to scale well), its pretty deceptive.

I'd agree with Red, he appears to be outright lying.

[ Edited by Jim 28.07.2020 - 15:51 ]

> I could see making a mistake once, but repeating it and and ignoring questions?

There's always the remote possibility that he missed the question, after all he didn't post any other comment to that news item after the question was posed. Else it's probably what Jim said in the first paragraph of comment #174.

> it would look better to be associated with the designers behind a successful
> ISA (68K), instead of one that in my opinion was a misstep by Motorola (88K).

Exactly. Btw, according to that PDF (page 12), Alsup joined Motorola only in ca. 1981 (or even only in 1983 according to his LinkedIn profile), so for that reason alone he couldn't possibly have co-designed the 1979-released 68000.

> their probable real legacy is a design that drove Motorola to IBM's door.

They never claimed their design to be based on the 68k, so it's not based on the 88k either just because a designer of the 88k architecture helped them with their project. Alsup also is a designer of the 2nd generation hyperSPARC and the chief architect of the AMD K9, yet Libre-SOC is obviously not based on any of them just because of that.

> why they mention the CDC 6600 is anyone's guess, since that's so old
> that it isn't likely that anything related to it is terribly relevant.

Libre-SOC's dynamic pipeline scheduling is based on the CDC 6600's scoreboarding algorithm. And that's precisely where Alsup has helped the project:

https://libre-soc.org/3d_gpu/architecture/6600scoreboard/

> laying claim to 68K and 6600 heritage

I can't see where they claim 68k heritage. And the CDC 6600 heritage is real, as far as I can see.

Interesting design idea, the scoreboard.

And Mitch seems to be fairly well versed on the 6600, from what I've seen in interviews.
Thanks.

> POWER10 postponed to 2021

POWER10 formally announced for "the second half of 2021":

https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor
https://www.youtube.com/watch?v=btbeXx6xXBU

Addendum:

> Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

Still no link to the spec, but some mention of Power ISA 3.0C in slides from ICS in June 2020 (page 2):

"April 2020 – POWER ISA 3.0c [...]
- Same as POWER ISA 3.0b except for
• Compliancy Subsets
• Custom Extension Space (Sandbox)
• SMF Feature"

(further mentions on pages 3 and 6)

Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg

Update:

> Project to be presented at XDC 2020 in September:
> https://xdc2020.x.org/event/9/contributions/607/

Also at OpenPOWER Summit NA 2020 two days earlier:

https://openpowerna2020.sched.com/event/eDqa/the-libresoc-initiative-a-hybrid-cpuvpugpu-luke-leighton-libresoc

Update:

> IBM has opened the A2 core:
> https://github.com/openpower-cores/a2i
> https://git.openpowerfoundation.org/cores/a2i

New core contribution hinted at:

https://openpowerna2020.sched.com/event/eDtC/new-core-contribution

I have a hunch it will be the PPC405. After all, IBM already opened the core to researchers and academia through Power.org back in 2006.

http://web.archive.org/web/20120722083542/https://www.power.org/news/articles/405download/

Update:

> "Microwatt [...] does not currently implement any floating-point or vector instructions,
> hypervisor mode, big-endian mode, 32-bit mode, or the HPT/SLB MMU facilities."
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/210525.html

Some weeks/days ago, Microwatt got big-endian mode, 32-bit mode and an FPU:
https://github.com/antonblanchard/microwatt/pull/239
https://github.com/antonblanchard/microwatt/pull/245

Update:

>> IBM has opened the A2 core:
>> https://github.com/openpower-cores/a2i
>> https://git.openpowerfoundation.org/cores/a2i

> New core contribution hinted at:
> https://openpowerna2020.sched.com/event/eDtC/new-core-contribution
> I have a hunch it will be the PPC405.

Okay, not the 405, but the pre-existing yet until now secret A2O, which compared to the well-known in-order A2I added out-of-order execution at the cost of being reduced from SMT4 to SMT2.

https://openpowerna2020.sched.com/event/eOyb/ibm-open-sources-the-a2o-core-bill-flynn-ibm
https://static.sched.com/hosted_files/openpowerna2020/39/Bill%20Flynn.pdf
https://www.youtube.com/watch?v=2IshMgIGCR4
https://openpowerfoundation.org/openpower-foundation-introduces-ibm-hardware-and-software-contributions-at-openpower-summit-2020/
https://github.com/openpower-cores/a2o
https://git.openpowerfoundation.org/cores/a2o
https://github.com/openpower-cores/a2o/blob/master/rel/doc/A2O_UM.pdf


Edit: added link to another repository

[ Edited by Andreas_Wolf 18.10.2022 - 13:15 ]

Update:

> [Libre-SOC] at OpenPOWER Summit NA 2020 [...]:
> https://openpowerna2020.sched.com/event/eDqa/the-libresoc-initiative-a-hybrid-cpuvpugpu-luke-leighton-libresoc

Slides available: https://static.sched.com/hosted_files/openpowerna2020/3e/The%20LibreSOC%20Initiative.pdf (video)

Page 7 has a strange claim:

"Next: create a low-cost test ASIC (180nm). (first OpenPOWER ASIC since IBM’s POWER9, 10 years ago)"

POWER9 10 years ago? 2010 was POWER7. POWER9 was 2017.

Interestingly, the claim was quoted and questioned in a discussion but this was again ignored while virtually everything else in that thread was addressed. Makes one wonder.


Edit: claim repeated in November

[ Edited by Andreas_Wolf 06.12.2020 - 22:08 ]

Quote:
Not too shabby for an embedded core. And certainly more advanced than the 405 (or the 440 of the Sam460 ex), being 32bit Power ISA v.2.03 cores (roughly POWER5), where the A2O is 64bit Power ISA v.2.07 (roughly POWER8).

But apart from being ISA v.2.07 compatible it does not seem to feature a SIMD vector unit (Altivex, VSX) nor an MMU? (klick)

> the 405 (or the 440 [...]), being [...] Power ISA v.2.03 cores (roughly
> POWER5), where the A2O is [...] Power ISA v.2.07 (roughly POWER8).

I really don't get this fixation on Power ISA revisions. The PPC405 or PPC440 are nothing like the POWER5+, even if both are Power ISA v2.03. And likewise, the A2O is nothing like the POWER8, even if both are Power ISA v2.07. The option-based way the Power ISA (except v3.0/v3.0B, which gave up on optionality) spec compliancy works (v2: categories; v3.0C/v3.1: compliancy subsets) makes the ISA revision mostly irrelevant for comparison of microarchitectures/cores. To illustrate my point, see if you can find any new feature in the v2.07 A2O compared to the v2.06 A2I that was added in Power ISA v2.07.
There's one extremely relevant thing with Power ISA versions, namely the turning point that IBM created with Power ISA v3.0 in 2015 (see comments #88, #163, #165, #167), which prevents Power ISA v2 Book III-E cores from being used commercially (i.e. hard core, ASIC) under the royalty-free OpenPOWER v3.0C or v3.1 licenses. Thus, the v2.06/2.07 A2I and A2O cores cannot be used commercially under the license by 3rd parties unless those cores be upgraded to ISA v3.0C or v3.1 level, which includes, among other things, replacing the embedded supervisor instructions (from Book III-E of Power ISA v2) by non-embedded ("server") supervisor instructions (from Book III-S of Power ISA v2, or from Book III of Power ISA v3 or pre-v2.03 PowerPC ISA). This is quite an effort.
As it stands, the commercial usability of A2I/A2O in the OpenPOWER context is not really there. IBM could have contributed not just Power ISA v3.0C and v3.1 but also old Power ISA v2 revisions to the OpenPOWER Foundation for 3rd party use, but they decided not to do this and I'm sure they have their reasons for this decision. Btw, IBM can as well open-source any of its Power ISA v2 Book III-S cores, like POWER5+ to POWER8, or any of its old pre-v2.03 PowerPC cores, like 40x (the 440 being the first IBM core with Book-E extensions), 6xx, 7xx, 970, Cell PPU (probably subject to consent by Sony and Toshiba, though), POWER3 to POWER5. Anything from that list is more compliant with Power ISA v3 than A2I/A2O is, and I'm still hopeful with regard to this.

> it does not seem to feature a SIMD vector unit [...] nor an MMU?

No SIMD, but basic MMU is there.


Edit: changed wording

[ Edited by Andreas_Wolf 05.10.2023 - 19:26 ]

Quote:
So CPUs compliant to the same ISA don't understand the same instructions? Seems a bit more complicated than I thought...

> CPUs compliant to the same ISA don't understand the same instructions?

Exactly, the Power ISA revision usually tells nothing about the supported instructions of the microarchitecture/core declared compliant with the respective Power ISA revision. With each new Power ISA revision, new optional features/instructions were added (exception: Power ISA v3.0 which killed entire Book III-E and Book VLE). Every new Power core was simply declared compliant with the ISA revision that was recent at time of release, no matter if it supported the new optional instructions or not. Usually, the big IBM POWER processors were the ones that supported the new instructions and that the new ISA revision was released for in the first place (exceptions: POWER5+/POWER5++ (ISA v2.03/v2.04) didn't implement VMX/AltiVec introduced with ISA v2.03, this took until POWER6 (ISA v2.05)). This way of assigning ISA revisions to cores has been legit as new instructions have always been optional. That's why a core declared compliant with a certain ISA revision is automatically compliant with all follow-up revisions (exception again: Power ISA v3.0).
This way, the very same ISA revisions are shared by
- cores with FPU and without
- cores with MMU and without
- Book III-S cores and Book III-E cores
- Book III-E cores with SPE and Book III-E cores without
- cores with VLE and cores without
- VLE cores with Book I-III instructions and VLE cores without
- cores with SIMD and cores without
- SIMD cores with VSX and SIMD cores without
- cores with AltiVec/VMX in both endians and cores with AltiVec/VMX only in big-endian
- 32 bit-only cores, 64 bit-only cores and 32/64-bit cores
- cores with decimal FP and cores without
- cores with transactional memory and cores without

These are just the most obvious instruction set differences. And to give you the most extreme example, both the e200z0 and the POWER5+ implement Power ISA v2.03, yet they do not have even one single instruction in common.

> Seems a bit more complicated than I thought

This graph is quite okay, but it has a major flaw: it implies that Power ISA v3.0 and above still contain Book III-E and Book VLE, which they do not. (As minor flaws, it falsely implies that Power ISA v3.0 and above have been released by Power.org, and it's missing Power ISA v3.0C.)

[ Edited by Andreas_Wolf 20.09.2024 - 13:41 ]

Addendum:

>> Power ISA "3.0C"? Never heard of that. Does anybody have a link to that "3.0C" spec?

> some mention of Power ISA 3.0C in slides from ICS in June 2020
> (page 2): [...] (further mentions on pages 3 and 6)
> Respective presentation: https://www.youtube.com/watch?v=0zIwLCnIuqg

Revised presentation from OpenPOWER Summit NA 2020:
https://www.youtube.com/watch?v=ZGvEpd4vNK0

Inexplicably, the occurences of "3.0c"/"3.0C" on pages 2/3 got replaced by "3.0", which is of course plain wrong as neither has Power ISA v3.0 from 2015 (or v3.0B from 2017) been contributed to the OpenPOWER Foundation nor does v3.0 (or v3.0B) have any compliancy subsets. Both things started only with v3.0C/3.1.
These changes to the slides must have been made deliberately. What the heck is going on there?


Edit: "V3.0C" mentioned in https://www.youtube.com/watch?v=SO8a8zcAiZc (at 13:00 and 20:04) and https://video.fosdem.org/2021/D.power/microwatt_grows_up.mp4 / https://video.fosdem.org/2021/D.power/microwatt_grows_up.webm (at 5:00 and 13:33)
(Btw, funny how Paul Mackerras in the first video at 11:45 claims that the ISA renaming in 2006 from PowerPC ISA (v2.02) to Power ISA (v2.03) by Power.org happened because Freescale allegedly had very much stopped using the ISA so that it was pretty much just about the IBM POWER line of server CPUs at that time (and in the second video at 4:18 that it happened because IBM allegedly was the only company using the ISA or making any new CPUs with it), when in fact the opposite is true, namely that the renaming represented the incorporation of the Book-E extensions (implemented by IBM PPC440/PPC460 and Freescale e200/e500 back then, which are embedded class and thus as un-POWER as possible) into the official ISA specification.)

[ Edited by Andreas_Wolf 18.02.2021 - 22:03 ]