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[ Edited by Velcro_SP 20.04.2011 - 06:51 ]

STOP, PLEASE! BOTH OF YOU!

> I responded briefly to your observation that the neighboring paragraphs
> "specifically" referenced 5121-based systems and its clear implication that
> therefore the middle one does too.

Yes, and by doing so you commented these paragraphs. That's why I don't understand that you asked me to not comment them either when in fact you did.

> I said that they also specifically reference other systems and so that
> logic really seems to lean the other way.

You are right. The 3rd paragraph mentions ACube systems specifically. Here I said something I didn't mean. Sorry for that. I was thinking of "mainly" when I wrote "specifically". My bad.

> I then said just post the paragraphs since you brought it up, don't further comment

Yes, you said that in the same posting where you yourself had commented them.

> and let others decide.

I don't think it's about any "others". At least not from my side. But of course it's a public discussion and anybody can take part in it, passively or even actively.

> You didn't say "main point" at the time. That's different from your "specifically."

Yes, you're right in that. See above.

> "Main point" requires reading and evaluation.

Yes, that would be my "short story".

> Before I do that, would you mind clarifying what your end point is? That I specifically
> advocated putting a PowerVR chip on a 5121e-based system and wasn't speaking
> of anything else at all?

No, but that you were also (and, by taking the two surrounding paragraphs into account, even mainly) speaking of MPC5121e based systems and thus also (or even mainly, see above) advocated putting a PowerVR chip on an MPC5121e based system.

> That you recognized I was speaking broadly but putting a PowerVR chip on
> a 5121e-based system was one possible outcome?

No.

> That maybe I wasn't advocating that at all, but you had fair reason at the time to
> believe it and did believe it because of the context and the words I used?

Short answer: No.
Long answer: The second part (after "but") would be "yes". The first part fails to regard the conceptual difference between "intending (not) to advocate" (which only happens in the author's mind) and "actually (not) advocate" (which is what is actually written down). As I can't read your mind (and also couldn't at that point in time of course) I cannot answer that question as a whole with "yes" because I'm confident that your actual *words* advocated (also, or even mainly) putting a PowerVR chip on a 5121e based system, which I objected to.

"I know you think you understand what you thought I said, but I am not sure you realize what you heard is not what I meant." Richard Nixon

"Mistakes are always forgivable, if one has the courage to admit them." Bruce Lee

[ Edited by Jim on 2010/8/10 20:58 ]

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[ Edited by Velcro_SP 19.04.2011 - 15:15 ]

Quote:

Making friends, I suppose.

Quote:

Not really, I am usually able to communicate with my friends and a "please stop" works. Here, I failed to make it apparent that the argument was totally boring and pointless. I'm sorry I "yelled".

> It's apparent that VSX is an extention of VMX. I got confused because those few times
> I read about VSX, I missed -or they omitted- VMX mentioned. And until now -that is
> until you made me read more about it :) - I thought they were distinctive units.

I found some more information there:

http://www.power.org/events/Power7/Performance_Guide_for_HPC_Applications_on_Power_755-Rel_1.0.1.pdf

Pages 7/8:
"A new single instruction multiple data (SIMD) instruction set called VSX is introduced in the POWER7 processor. This is in addition to the AltiVec SIMD instruction set which was previously introduced in the PPC970-based system, the JS20 blade server."

Page 69:
"The Vector-Scalar floating point eXtension architecture (VSX) has been developed by IBM to extend SIMD support to include two independent 2-way-SIMD double precision floating point (FP) operations per cycle. The Altivec SIMD features are a subset of VSX. [...] For POWER systems, the "VSX" term has been used to highlight the double precision arithmetic instructions supported by the POWER7 hardware, with "Altivec" reserved for the older 32-bit precision arithmetic SIMD support."

Page 71:
"The POWER7 architecture continues to support the Altivec instruction set, and extends support to double precision floating point operations with the VSX instruction set. The VSU (Vector Scalar Unit) is the hardware that implements the Altivec, VSX and scalar floating point instructions. There are no longer separate scalar FPUs in the POWER7 core. [...] The VSU is the combination of the Altivec execution unit and the 4 FPUs. It is divided into two independent pipes, each of which can execute one instruction per cycle. Each pipe can independently execute a scalar double-precision FP op or a SIMD double-precision FP op. All SIMD operations are on 16-byte vectors of data. Mimicking the behavior of the original Altivec unit, pipe0 handles the simple FX, complex FX and 4-way SIMD single-precision FP ops and pipe1 handles the Altivec permute ops."

Page 83:
"While Altivec and VSX have differences in programming details, they have similar criteria when it comes to deciding how to convert a candidate (scalar) program to exploit SIMD instructions to increase performance."

Page 86:
"The vector multiply-add intrinsic for double precision arithmetic (VSX) is the same as for single precision (Altivec). Not all corresponding VSX and Altivec instructions share the same intrinsic."


Taking these notes into account, my conclusions are as follows:

1. VSX and VMX/AltiVec are really two distinctive physical units.
2. The features of VSX represent a superset of the features of VMX/AltiVec.
3. The VSX instruction set is *not* a superset of the VMX/AltiVec instruction set. In fact, the instruction sets are different (with some overlapping). That means that a processor implementing VSX does not necessarily implement VMX/AltiVec. A program using VMX/AltiVec instructions will therefore not run on a processor that implements just VSX, but can be changed on source code level to use VSX instead.

Any objections? ;-)

>The VSU (Vector Scalar Unit) is the hardware that implements the Altivec, VSX and scalar floating point instructions.>

I don't know, Andreas. From that statement, I would gather that all floating point operations are performed by one hardware unit designed the execute all three of sets of instructions.
While these instructions could be implemented separately, they don't appear to have been in Power7.
Therefore, VSX isn't a superset of the VMX/Altivec instructions, and would appear to act like many of the instructions added over the years to X86 processors.
There are many old X6 instructions (including many old math coprocessor routines) that remain in the architecture (and allow for backward compatibility) that have been rendered irrelevant by newer, more powerful instructions.
While a new PPC processor might be designed to only support VSX, it seems unlikely that IBM would want to do that.
You are certainly right in your assertion that VSX is a new group of instructions with only some overlap of older Altivec instructions. That limited duplication of functions and the fact that all former instructions are implemented in Power7 would indicate that IBM wants to continue to support full backward compatibility (as they have done with revisions in the past).

I don't know what you define as a superset, but if Altivec is equivalent to Intel MMX , then VSX can be see as an analog of the later SSE instruction sets.

[ Edited by Jim on 2010/8/10 21:28 ]

One question you might be able to address, Andreas. Why does everyone discount the idea of Power7 being moved into mainstream markets? When Apple required something more advanced than the G4 level processor, the processors that were eventually designated as G5s were designed incorporating features from higher end Power systems. Even the mass market Cell architecture gains some power from similar incorporations.
If IBM were again to target a large consumer market, why wouldn't they base the product on their most powerful design yet? Isn't that sort of what they've done in the past?

[ Edited by Jim on 2010/8/11 2:19 ]

> I don't know, Andreas. From that statement, I would gather that all
> floating point operations are performed by one hardware unit designed
> the execute all three of sets of instructions.

Read further: "The VSU is the combination of the Altivec execution unit and the 4 FPUs." I read it as the VSU consisting of smaller (sub-)units like for instance the AltiVec unit. But maybe I'm just reading it wrong and it means that the VSU is now what "the Altivec execution unit and the 4 FPUs" had been before, i.e. in former implementations like POWER4/5/6 or PPC970.

> Therefore, VSX isn't a superset of the VMX/Altivec instructions

Yes, that's what I concluded, regardless of VSX and AltiVec being two distinctive physical units or being both executed by just one single unit.

> While a new PPC processor might be designed to only support VSX,
> it seems unlikely that IBM would want to do that.

Yes, but it's not only IBM I'm looking at. See (last sentence):

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=7001&forum=3&post_id=74716#74716

> I don't know what you define as a superset

http://en.wikipedia.org/wiki/Subset#Definitions

> but if Altivec is equivalent to Intel MMX , then VSX can be
> see as an analog of the later SSE instruction sets.

That sounds reasonable.

> Why does everyone discount the idea of Power7 being moved into
> mainstream markets?

Is anybody really doing this? :-) While the POWER7 "as is" is definitely not suited for our market(s) a trimmed down (features, power usage, cost) version surely could be. That's exactly what IBM did with the POWER4 after all.

> When Apple required something more advanced than the G4 level
> processor, the processors that were eventually designated as
> G6s were designed incorporating features from higher end
> Power systems.

I take it you mean "G5", not "G6". And yes, the PPC970 aka G5 is a trimmed down POWER4.

> Even the mass market Cell architecture gains some power
> from similar incorporations.

BigGun says that the Cell PPE architecture (while being way older, so it's probably the other way round) is related to the POWER6 architecture:

http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=29336&forum=2&start=180#504967

> If IBM were again to target a large consumer market, why wouldn't
> they base the product on their most powerful design yet? Isn't that
> sort of what they've done in the past?

Yes, exactly. But the real question is: Are IBM to target a large consumer market ever again with Power Architecture (not counting developments solely done for Microsoft or such)? :-)
However, there is something going at IBM regarding alleged trimmed down POWER7 cores:

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=6268&forum=11&post_id=75659#75659

I'm not sure if The Register is right though, because POWER7 is an out-of-order design while the A2 seems to be in-order. But the A2 core based PowerEN processor doesn't seem to be suited for our market(s) either, unfortunately.

No, I think I've seen mention of the A2 before and the impression I got was that IBM had designed it for specialized tasks like the network processors that Freescale has focused on.

Lately it seems like a lot of the PPCs introduced aren't really well suited to our market. Its become hard to argue with AOS fans about the PA6T (not that I try to), when floating point support is so weak on a large number of other new PPCs that have been introduced.

Thanks for pointing out the error on that post. I corrected it as, obviously, there was never a G6.

[ Edited by Jim on 2010/8/11 2:20 ]

[ Edited by Jim on 2010/8/11 2:45 ]

> I think I've seen mention of the A2 before

Definitely. Wikipedia has been listing the A2 since December 2008 (back then in the PPC4xx article due to little known information, removed from there in January 2010):

http://en.wikipedia.org/w/index.php?title=PowerPC_400&diff=256023621&oldid=252665140
http://en.wikipedia.org/w/index.php?title=PowerPC_400&diff=339861948&oldid=335616824

I mentioned the A2 first here on MorphZone in March 2009:

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=6268&forum=11&start=40

> the impression I got was that IBM had designed it for specialized
> tasks like the network processors that Freescale has focused on.

Yes, that's also my impression. To date no availability or even pricing information for the PowerEN is known to me, but maybe the idea to build something desktop-like around it wouldn't be much worse than to use QorIQ P3/P4/P5 for that purpose ;-)

>> Over there on the Bunny minator claims:
>> "AMCC cancelled Titan"
>> http://moobunny.dreamhosters.com/cgi/mbmessage.pl/amiga/174889.shtml
>> Do you think that could be true?

> No Applied Micro's not about to give up on Titan.

There's again an interesting posting by minator:
http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=32137&forum=2#574839

Some quotes regarding Titan:

"Titan is [...] a completely new core design."

I'm eager to see where this statement leaves Lauterbach's hint that Titan is PPC450 based.

"Titan has been killed. Titan was actually designed by a company called Intrinsity*. Apple bought Intrinsity and suddenly Titan is no more. [...] *I went to a presentation by Intrinisity where they said this."

Here we have minator's "Titan is dead" claim again.

"The new Titan core design will not die, it will reappear at a later date."

That's a confusing one for me. Just before he said that Titan was killed, to say one line further down that it's not been killed at all. Do I miss something here?

No, you're not the source of this confusion, minator does appear to say Titan has been killed and that it will reappear later. He seems confused.

His confusion over Intrinsity's part in the designing of Titam is understandable

If your follow Applied Micro's press releases, you would be under the impression that Titan's low power draw 90nm construction was a result of AMCC's licensing of Intrinsity's Fast14 Technology.

Intrinsity's own press releases lay claim to far more responsibility in the design.

http://www.marketwire.com/press-release/Intrinsity-Nets-2-GHz-4000-DMIPS-PowerPC-FastCore-733747.htm

Since the Titan core is not a stand alone product, and it has already been announced as part of an SOC to be produced this year, I don't think the core is dead.

Too much has been speculated based on limited information coming from sources that, primarily, appear to want to emphasize their role in developing the product.

Intrinsity's has a right to be proud of its innovative gating and timing designs. These schemes are unique and are responsible for allowing the 90nm processor to scale up its clock speed while remaining a low draw component.

However, AMCC and Intrinsity may be overplaying the actual changes in architecture. Except for higher clock speed, Titan doesn't appear to offer any radical improvements over AMCCs current processors. Their claim that "No other 32-bit PowerPC core even comes close to the 2.0 GHz 4000-plus DMIPS performance of this core" seems questionable in light of the MIPS figures you've posted.

The comparisons to AMCC's PPC460 core may turn out to be valid. The designers of this chip had to start somewhere and considering both companies past histories, an evolutionary design seems more likely than a completely revolutionary approach.

Just getting Fast14 incorporated into the design would have been difficult enough.

> minator does appear to say Titan has been killed and that it
> will reappear later. He seems confused.

Thanks. I'm glad it's not me missing something obvious. Yet I'd like to know what he really meant. I think he can't seriously contradict himself in such an obvious way that it's almost frightening ;-)

> If your follow Applied Micro's press releases, you would be under the impression
> that Titan's low power draw 90nm construction was a result of AMCC's licensing of
> Intrinsity's Fast14 Technology.

Yes, that's the impression I've been under.

> Intrinsity's own press releases lay claim to far more responsibility in the design.

Indeed. There appears to be some kind of coherency gap between the two press releases.

> it has already been announced as part of an SOC to be produced this year

According to Applied Micro's October 2009 press release the APM83290 has been supposed to enter production in Q1 2010. This means that this SoC should now have been in production for at least 4.5 months already. So far I haven't spotted any statement regarding production delay let alone any existing device using this SoC. With each day passing without any new information minator's assessment becomes more and more probable, I fear.

> Too much has been speculated based on limited information coming from sources
> that, primarily, appear to want to emphasize their role in developing the product.

Without new information from either Intrinsity (unlikely because of having been bought by Apple) or Applied Micro there's not much more we can do except to speculate ;-)

> Their claim that "No other 32-bit PowerPC core even comes close to the
> 2.0 GHz 4000-plus DMIPS performance of this core" seems questionable
> in light of the MIPS figures you've posted.

Yes, depends on the definition of 'close' I guess. At 1.7 GHz (maximum clock rate as specified by Freescale) the e600 delivers 3910 DMIPS. It seems that about 2% less performance doesn't qualify as being 'close' ;-)

> The comparisons to AMCC's PPC460 core may turn out to be valid.

As I pointed out, Lauterbach lists the Titan core based APM83290 as being "PowerPC 450". On the other hand, they list both the PPC460EX and PPC460GT as being "PowerPC 460", ignoring the fact that these two SoCs actually have a PPC440 core. So maybe Titan was developed from the PPC460 core even, and Lauterbach got that wrong as well. Should the APM83290 really be based on an upclocked PPC460 core then there's the question what the APM821xx (which should have been in production for at least 1.5 months according to the announcement press release, but is only really sampling for now) was needed for in comparison.

I thought that when they announced the APM83290 they were moving from sampling to full production rather quickly (faster than many larger companies).
Perhaps the delay reflects a needed revision in their die. That could certainly account for a significant delay. Its difficult to know in the vacuum that surrounds this product. Applied Micro has never even mentioned this core on their website and most of the information currently available has come from press releases.

No one outside of their AMCC's NDA has any really hard data on this product. At least when Freescale announced the e5500 they published a block diagram showing the major parts of that core.

> I thought that when they announced the APM83290 they were moving from sampling
> to full production rather quickly (faster than many larger companies).

Less than 6 months for sampling is rather quick, yes. I guess that would have made up for the 2.5 years that passed from the announcement of the core to the announcement of the processor based on that core ;-) Btw, both the APM801xx and APM821xx are/were supposed to have an even shorter sampling phase of no more than 3 months according to the announcement press releases.

> Applied Micro has never even mentioned this core on their website

Apart from both the Titan press release (May 2007) and the APM83290 press release (October 2009) on appliedmicro.com there're some old product selector guides mentioning Titan:

http://www.appliedmicro.com/Embedded/PPC-ProductSelectorGuide_v7-01.pdf (October 2007)
http://www.appliedmicro.com/Embedded/ppc_psg_7%2002_111607web.pdf (February/March 2008)
http://www.appliedmicro.com/Embedded/ppc_psg_7.3_092908.pdf (September 2008)

See the roadmaps on each of these document's page 3 (and compare to the "roadmap" on page 4 of the most recent product selector guide (April/May 2010)).

> most of the information currently available has come from press releases.

I think the presentation PDF files scattered around the web and especially on power.org are much more informatory (including Titan block diagram) than the press releases:

http://www.google.com/search?q=site:power.org+amcc+titan+filetype:pdf

> At least when Freescale announced the e5500 they published a
> block diagram showing the major parts of that core.

The Intrinsity press release you linked to comes with a Titan block diagram (on the top right, but the link to the bigger version of the image is dead).


Edit:

Now I know what minator refers to and it's all making sense now. It's true: Titan is dead :-( Seems we're some weeks behind, Jim ;-)

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=6268&forum=11&post_id=75800#75800

[ Edited by Andreas_Wolf on 2010/8/13 2:01 ]

Quote:

Exactly. I think Jim has "too much" faith in POWER coming back to consumer space. In this business, when something is abandoned, it NEVER comes back. Well, go tell that to Escom, Gateway, Bill McEwen...

Quote:

That URL doesn't show me the post you want. It might be that I chose "most recent at top" in my MorphZone forum preferences. But this different URL worked:

https://morph.zone/modules/newbb_plus/viewtopic.php?topic_id=6268&forum=11&post_id=75659

See that "75659" now as the parameter "post_id", instead of the hash (#).

> POWER

Just a small hint at terminology: POWER is IBM's server CPU microarchitecture implementing the Power ISA (instruction set architecture) launched in 2006 as successor to the PowerPC ISA. See:

http://en.wikipedia.org/wiki/Power_Architecture#Glossary

> That URL doesn't show me the post you want. It might be that I chose
> "most recent at top" in my MorphZone forum preferences.

Yes, that's the reason. Thanks for pointing it out. I'll make my internal links more compatible from now on, using your URL pattern (plus fragment identifier).

> See that "75659" now as the parameter "post_id", instead of the hash (#).

The "#<number>" is needed nevertheless because it works as a fragment identifier.

Quote:

> Freescale has just released a 64bit successor to the e500, thr e5500.

It's not released yet, just announced.

> IBM has a processor based ion the P7

That's what The Register claims at least. As I said, I'm not really convinced that PowerEN is really POWER7 based (see in-order vs. out-of-order execution).

> AMCC is carrying forward a 40nm variant of their Titan core without
> Intrinsity's Fast14 technology.

As far as I understand, the new 40 nm core that is supposed to substitute the scrapped Titan core won't be a Titan variant but another core altogether, offering similar features. I'd be disappointed if the undisclosed 40 nm core really is supposed to just be Titan with a shrinkage applied to it to make up for the abandonment of Intrinsity's Fast14 technology.

> It is even rumored that the next PlayStation portable will be Cell based.

That rumour is utter nonsense. The PSP2 will most likely be nVidia Tegra 2xx (ARM Cortex-A9 core) driven.

http://www.semiaccurate.com/2010/07/14/sonys-psp2-powered-nvidias-tegra-line/

> Freescales planned e5500 cored products may be fast (Mips) than that
> processor or Titan.

In terms of DMIPS the e5500 will *definitely* be faster than the sinked Titan or a single PA6T core.

Quote:

Personally, I's settle for a Titan derived processor without Fast14. At 40nm it might scale fairly well. Even a 1.8 Ghz variant could be much more powerful than AMCCs current line.

Until we see first hand the floating point capabilities of Freescales planned e5500 core, the (DMIPS) disadvantage of the Titan (or its successor) may not be as great as we're assuming.

More than any other factor, the comparative price of e5500 cored and Titan cored processors and their availability may affect what products each is incorporated into.

I could see a 1.8Ghz "Titan" based motherboard, if the cost could be kept down, making a nice substitute for Acubes product line or as an alternative to a Pegasos or Mac.

> Personally, I's settle for a Titan derived processor without Fast14. At 40nm
> it might scale fairly well. Even a 1.8 Ghz variant could be much more powerful
> than AMCCs current line.

While the APM83290 was supposed to run up to only 1.5 GHz, the Titan core itself was announced to scale up to 2.0 GHz. I expect a Titan replacement core to not undercut that figure, and the Titan replacement core based processor should really not undercut the 1.5 GHz figure of the APM83290. So yes, 1.8 GHz would be fine for the processor I guess, and you're right that it would definitely be much better performing than anything they have right now, be it officially announced or sampling or in volume production.

> Until we see first hand the floating point capabilities of Freescales planned
> e5500 core, the (DMIPS) disadvantage of the Titan (or its successor) may
> not be as great as we're assuming.

I really don't get your point here. The DMIPS per MHz figures of both the e5500 and the Titan are officially known: 3.0 vs. 2.0. That's 50% more DMIPS per MHz for the e5500. So to get on par the Titan would have to be clocked 50% faster than the e5500, which it is not. Quite to the contrary, the e5500 is announced to scale to a 25% higher clock rate than the Titan (or even 47% if we look at the announced processors based on the cores). That's a 87.5% higher DMIPS performance altogether for the e5500 (and even 120% higher on a processor level).
Of course that's all assuming that the Titan replacement core will deliver the same DMIPS per MHz figure as Titan, which would be the case if it's really just a shrinked Titan without Fast14.

> I could see a 1.8Ghz "Titan" based motherboard [...] as an alternative to a [...] Mac.

An "alternative" to a G4 Mac as in "similar performance", yes.