Update:

> Power ISA 3.1B spec released as of September 2021.

Power ISA 3.1C spec released today:

https://files.openpower.foundation/s/9izgC5Rogi5Ywmm/download/OPF_PowerISA_v3.1C.pdf
https://openpowerfoundation.org/specifications/isa/

Update:

> it's now actually announced to be another CPU called S1 by a
> chip design company called Solid Silicon

Solid Silicon has joined the OpenPOWER Foundation as platinum member:
https://openpowerfoundation.org/members/solidsilicon/

...and it has raised 100,000 USD in a funding round in February:
https://www.crunchbase.com/organization/solid-silicon/company_overview/overview_timeline

Thanks for sharing @Andreas_Wolf!

Good to hear news from Solid Silicon S1! This will be the CPU powering Raptors upcoming Blackbird II & Talos III series (klick).

PCIe 5.0, DDR5 RAM, SMT-4, Bi-Endian, 32/64bit does not sound shabby either. Also looks like Power ISA 3.1C does not deprecate any features over the POWER9 so it should run G4/G5/POWER9 built code just fine.

> Solid Silicon S1 […] will be the CPU powering Raptors upcoming
> Blackbird II & Talos III series (klick).

Yes, see comment #240 :-)

> looks like Power ISA 3.1C does not deprecate any features over the
> POWER9 so it should run G4/G5/POWER9 built code just fine.

I'm not sure if S1 will implement 3.1C or an older/newer specification. What we know at least is that Power11 will necessarily implement the same ISA spec as Power10 (see comment #248), which should be 3.1B.

Update:

> Solid Silicon has joined the OpenPOWER Foundation as platinum member: [...]

Today's press release reveals that the CTOs of Raptor CS and Solid Silicon are one and the same Pearson ;-)

Solid Silicon runs a public GitLab repository where Pearson (who is also the OpenPOWER Foundation's Chairman now) is active:
https://gitlab.solidsilicon.io/public-development/open-source
https://gitlab.solidsilicon.io/tpearson

Addendum:

>> First test chip tape-out (180nm) is claimed to be a mere 5 days away

> Took a little longer:
> https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/

Years later, the first public pictures I'm aware of:
https://en.wikipedia.org/wiki/Libre-SOC#Hardware_implementation
https://commons.wikimedia.org/wiki/File:LibreSOC_M7_7945_2692_01.jpg
https://commons.wikimedia.org/wiki/File:LibreSOC_M7_7945_2692_02.jpg

> Good to hear news from Solid Silicon S1!

It's been quiet on this front, maybe too quiet. Solid Silicon has had (semi-)public appearances recently:

OCP Global Summit:
https://openpowerfoundation.org/events/ocpnasummit2024/

IBM TechXchange:
https://openpowerfoundation.org/events/ibmtechxchange24/
https://reg.tools.ibm.com/flow/ibm/techxchange24/sessioncatalog/page/sessioncatalog?tab.sessioncatalogtabs=option_1601178495160&search=4158

I've yet to come across any OpenPOWER or Solid Silicon coverage, videos or slides from these events.

Update:

> Solid Silicon has had (semi-)public appearances recently:
> [...]
> IBM TechXchange:
> https://openpowerfoundation.org/events/ibmtechxchange24/
> https://reg.tools.ibm.com/flow/ibm/techxchange24/sessioncatalog/page/sessioncatalog?tab.sessioncatalogtabs=option_1601178495160&search=4158
> [...]
> I've yet to come across any OpenPOWER or Solid Silicon coverage,
> videos or slides from these events.

Some text and image coverage has emerged:

"OpenPOWER Foundation’s newest Platinum member, Solid Silicon, presented their latest developments and roadmap for the first truly self-sovereign open computing platform based on POWER architecture."
https://www.linkedin.com/posts/openpower-foundation_techxchange-ibmtechxchange-linux-activity-7256733371400175616-Yhou

"OpenPOWER Foundation team showcased Solid Silicon innovations using OpenPOWER cores, which are crucial to enhancing open-source flexibility and performance. These OpenPOWER cores contribute to a highly modular and powerful architecture, supporting AI workloads and advanced data processing needs with efficiency and interoperability."
https://www.linkedin.com/posts/solid-silicon_activity-7256671325396578304-Nado

"Solid silicon team presented their product features which will be available in a year from now. [...] With a solid roadmap and the promise of product features rolling out in the next year, it seems like there's significant momentum in expanding open-source hardware capabilities [...] Here’s a breakdown of what they plan to release or achieve: [...] Solid Silicon aims to introduce self-sovereign chips that give enterprises full ownership and control over their infrastructure. This approach involves releasing open-source chips with open firmware, tools, and keys, allowing organizations to maintain and secure their infrastructure independently. [...] OpenPOWER CPU cores built on the POWER ISA, which are more open and customizable than proprietary chips."
https://www.linkedin.com/pulse/exploring-innovations-ibm-techxchange-2024-ganesan-narayanasamy-gkhhc

Thanks for the update Andreas!

Unfortunately this new info says nothing concrete at all about the actual S1 CPU cores or the current state of development...

> Unfortunately this new info says nothing concrete at all about
> the actual S1 CPU cores or the current state of development...

Yes, sadly. But there's some more (in the second paragraph of the quote):

"there will be opensource Power10-compatible CPUs available. The plan is that they will come next year. [...] Solid Silicon [...] promises to deliver these new opensource Power10 CPUs.
[...] There are plans to produce OpenPOWER board in Raspberry Pi format. But unfortunately the plans have no delivery date now. Todd confirmed that they know the need for such device and work on it."
https://blog.power-devops.com/p/if-you-are-in-the-us-you-probably

Of course, it's not the S1 chip itself that will be open source, but its firmware(s) will be. And it seems the PowerPi/POWERπ plans not mentioned for over a year (comment #231) are not quite dead yet.

...and then the Power11 slides:
https://community.ibm.com/HigherLogic/System/DownloadDocumentFile.ashx?DocumentFileKey=8a2968b0-523e-41ea-a817-0192e801a91a&forceDialog=0 (p. 8-15)
http://itjungle.wpenginepowered.com/wp-content/uploads/2024/11/tfh111324-story01-fig01.jpg
http://substack-post-media.s3.amazonaws.com/public/images/0eaa7c10-8b37-4f6a-899e-cf21603ca4f5_4054x2262.png

Addendum:

>> Unfortunately this new info says nothing concrete at all about
>> the actual S1 CPU cores or the current state of development...

> "there will be opensource Power10-compatible CPUs available. [...]
> Solid Silicon [...] promises to deliver these new opensource Power10 CPUs."
> https://blog.power-devops.com/p/if-you-are-in-the-us-you-probably

Page 12 of this presentation has some info on the S1 CPU (probably taken from Solid Silicon's TechXchange slides, which I so far haven't found a public link to), which say that it will have 18 or 30 Power10 cores. To me this seems to indicate that there's been no CPU core development at Solid Silicon, which isn't necessarily a bad thing as IBM cores' reliability couldn't be matched anyway. This would leave the on-chip controllers or even just their firmware as points of differentiation from IBM Power10 CPUs (as well as non-technical matters like price, availability etc., of course).

Quote:

Its great news IF it results in:

a) Cheap single core latest POWER derived CPU we could use to replace G5
b) Cheap X4 and x8 core POWER derivates
c) PPC32 to PPC64 FPGA cores as backup solution if all PC Sillicons die

I hope there are interestees and such licences are possible.

>> IBM Opens Up POWER Architecture For Licensing

> Its great news […]

No, it's from 2013, and its purpose has since then substantially changed from just licensing the POWER/Power microarchitecture (at cost) to also licensing the Power ISA (free of charge).

> IF it results in:
> a) Cheap single core latest POWER derived CPU we could use to replace G5

Single-core CPU derived from POWER9 or Power10 won't happen. Even the last G5 (PPC970MP) wasn't single-core any more.

> b) Cheap X4 and x8 core POWER derivates

Those wouldn't have to be derived from POWER/Power microarchitecture. Since 2020, it's possible to license the Power ISA v3.0C (or later) free of charge and develop a core/microarchitecture implementing the ISA.

> c) PPC32 to PPC64 FPGA cores as backup solution if all PC Sillicons die

Microwatt has been there for years.

> I hope there are interestees and such licences are possible.

I recommend to read not just the initial posting but also the thread (which you probably did to some extent seeing you already took part in it twice before) to learn what happened since 2013, especially regarding licensing of the POWER/Power microarchitecture and of the Power ISA.

Update:

> Microwatt got big-endian mode, 32-bit mode and an FPU

"Microwatt now supports almost all of the features of the SFFS (Scalar Fixed-poin and Floating-point Subset) compliancy subset of Power ISA version 3.1C [...]. It is also now SMP-capable"
https://lists.ozlabs.org/pipermail/linuxppc-dev/2025-January/280852.html

Update:

> S1 by a chip design company called Solid Silicon

S1 no longer mentioned on the website. What gives?

Update:

> the v2.06/2.07 A2I and A2O cores cannot be used commercially under the
> license by 3rd parties unless those cores be upgraded to ISA v3.0C or
> v3.1 level, which includes, among other things, replacing the embedded
> supervisor instructions (from Book III-E of Power ISA v2) by non-embedded
> ("server") supervisor instructions (from Book III-S of Power ISA v2, or
> from Book III of Power ISA v3 or pre-v2.03 PowerPC ISA). This is quite an effort.

From the president of the OpenPOWER Foundation:

"Call for Interns: Help Bring the A2O Core to Power ISA 3.X Compliance! [...]
Join Us in Building the Next-Gen #OpenPOWER Core — From RTL to Silicon
We are offering a select set of internships for highly qualified and motivated students to participate in a cutting-edge open hardware initiative: making the open-source A2O core compliant with Power ISA 3.0C/3.1C. [...] The #A2O core is a high-performance, out-of-order, dual-threaded 64-bit core originally designed for Power ISA v2.06. Our goal is to modernize this architecture to comply with Power ISA v3.X, enabling it to run modern Linux distributions and participate in #OpenPOWER-based innovations.
You'll work on: Enhancing instruction support (e.g. prefixed 64-bit instructions, SCV syscall interface, new arithmetic/logical ops)
- Updating the MMU to support radix-based page tables
- Adding VMX/VSX support (for Linux Compliancy Subset)
- Refactoring the interrupt model to match Power ISA Book III-S
- Replacing deprecated or legacy SPRs and instructions
- Modifying the debug and performance monitoring systems"
https://www.linkedin.com/pulse/call-interns-help-bring-a2o-core-power-isa-3x-ganesan-narayanasamy-jgq1e

Regardless of whether this is justified or not, they have to be aware of the terrible optics of "chips designed by interns".

> they have to be aware of the terrible optics of "chips designed by interns".

Absolutely. Besides, I doubt that anything tangible will come to fruition using this approach.

Quote:

It's an "open source" project that can be used as a study credit. Nothing special about that, I'm sure we all use SW (and to a lesser degree HW) that was developed with that model every day.

@Kronos

Quote:
Software bugs are bit easier to fix than hardware ones though.

Quote:

Sure, but so what?

I'd say verifying a new CPU is easier than any big SW project.

Both of which will come with plenty bugs and exploits often only found decades later even if developed by "professionals".

@Kronos

Got it. You think looking for interns is a great sign for the future of OpenPOWER.

I have nothing to add to that.

No, I think doing it or not doing it is a total nothingburger for such a project.