New multithreaded e6500 core with AltiVec technology
  • Yokemate of Keyboards
    Yokemate of Keyboards
    Andreas_Wolf
    Posts: 10449 from 2003/5/22
    From: Germany
    Update:

    >> How many PCI lanes does the T4 support?

    > AFAIK information about the number of PCIe (note the "e", legacy PCI is not supported)
    > lanes is not public yet. What's been revealed is the number of SerDes lanes, of which
    > some will be configurable as PCIe lanes (16 at best in case of T4240, 12 at best in
    > case of T4160; but due to SATA controllers will have to be decreased by 1 or 2 in both
    > cases), and the type and number of the PCIe controllers

    According to http://www.freescale.com/files/training/doc/dwf/DWF13_APF_NET_T1284.pdf (page 16), it's indeed possible with the T4240 to have up to 16 SerDes lanes for PCIe using either 2 controllers (x8 x8), 3 controllers (x8 x4 x4) or 4 controllers (x4 x4 x4 x4), whereas each controller can be downgraded to use less lanes. Those configurations would be without SATA though.
    Using 2 lanes for SATA leaves 14 lanes for PCIe, which can be configured as using either 3 controllers (x8 x4 x2) or 4 controllers (x4 x4 x4 x2).
    While two out of the T4's four PCIe controllers support PCIe 3 standard, the following restriction is mentioned by Freescale:

    "8 Gbaud is not supported with x8 link width"
    http://www.freescale.com/files/training/doc/dwf/DWF13_Designing_QorIQ_Hardware_SanJose.pdf (page 51)

    This means that whenever a PCIe3-capable controller of the T4 is being assigned 8 lanes, it switches from PCIe 3 to PCIe 2 standard, reducing the bandwidth of those lanes to about a half.

    Edit:
    http://www.freescale.com/files/training/doc/ftf/2014/FTF-NET-F0031.pdf has some more info on page 31/32:

    Using 16 SerDes lanes for PCIe, the following configurations are possible:

    1. x8-gen2 x8-gen2
    2. x8-gen2 x4-gen3 x4-gen2
    3. x4-gen3 x4-gen2 x4-gen2 x4-gen2
  • »21.11.13 - 14:57
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