Update:

>> Can you find out if it offers more PCIe lanes than the e5500?

> PCIe controllers in a SoC are not dependent on the SoC's core. If I take
> your question to mean whether the SoCs incorporating the e6500 core
> will have more PCIe lanes than the P5020 and P5010 then I'm afraid no
> such information is public yet. The only e6500 based SoC that got
> announced so far is the T4240, but no too specific information on that.

"The QorIQ T4240 [...] is the first AMP series device scheduled for release in 2012 and [...] integrates twelve e6500 cores in a single device that are organized into three processor clusters of four cores each. The 24 virtual cores are able to operate at up to 1.8 GHz [...]. New functions of data decompression/compression accelerator [...], Interlaken Look-Aside [...], PCIe 3.0, SR-IOV end point and data center bridging [...] are new with the T4240 processor."
http://www.freescale.com/files/32bit/doc/brochure/PWRARBYNDBITSQIG.pdf (page 3)
http://www.freescale.com/files/32bit/doc/brochure/PWRARBYNDBITS.pdf (page 13)

So while I'm not much wiser regarding the number of PCIe lanes yet (the document linked there mentions "2x 18-Lane SerDes (6GBaud and 11Gbaud)" for the QorIQ T4 but I'm not sure what that implies for PCIe if anything), we now know that it will be PCIe 3.0 lanes, i.e. doubling the per-lane bandwidth of the QorIQ P5's PCIe 2.x lanes.