The X5000 is more of a sideways move, not a forward move, from the X1000's performance level, that fact was established years ago.

Quote:

I actually preferred the X1000's expansion slot setup as the P50xx doesn't offer as many PCI-E lanes, and the fact that the PA6T has AltiVec instructions is a plus.
I don't think the PA6T core is quite as nice as the e6500 core, but it had some advantages over the e5500.

And the Gen2 PCI-E lanes, SATA2 capability, and DDR3 off the e5500 SOCs are already becoming dated, when compared to current CPUs.

I'd still favor the X5000 over the X1000, but the memory benches are disheartening. I wonder if these can be improved with better firmware.

If the choices are hoping for an X64 shift that appears to be stagnant, waiting for support for X5000 and MorphOS 3.10, sticking with what we have, or hoping for PCI-E G5 support (or some other RISC solution)...

I'm not surprised we're losing users.

David - Have a good time @ AmiWest. My guess is the focus may be the A1222.
The teething issues with the X5000 are actually to be expected, and some of these things will improve.
From what I have been able to tell, the X5000/40 should be ready for release soon.
Since that will offer twice the core count of the X1000, that's the model I really think makes more sense.

And, of course, I still like the goals of the T2080 laptop project.

Hopefully some solutions to utilizing the additional cores available on newer systems will eventually become available.

[ Edited by Jim 13.09.2017 - 03:00 ]

> topo

One of the first two squares of the 2nd PCIe controller is surely the PCIe-PCIe bridge, which creates 8 output lanes from 4 input lanes (see block diagram in the Cyrus Plus technical reference manual as well as the first link I gave you in comment #64).

> My X1000 [...] is using the e6500 core (I think)

It is not, of course. Freescale announced their e6500 in 2011, which was short of 6 years after P.A. Semi announced their PA6T. More info there:

https://en.wikipedia.org/wiki/PWRficient
https://en.wikipedia.org/wiki/PowerPC_e6500
https://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-platforms/e6500:E6500

> instead of the "weaker?" e5500, e600, or any other PPC core design.

Whether or not PA6T is stronger than e5500 or e600/G4 is surely open to debate and very much depends on the considered performance aspects (integer vs. floating point, cache etc.).

Andreas
this image was made by me some time ago because what i did not understand why they dint use the 3th pcie controller of the P50xx and you explain me so,me post ago.
for them was best made two different board one for 5020 and one for 5040 put less slots and dont use pcie-pcie bridges and use the 3 pcie controller im sure like this the machine will be have all better.

first and second square on the second controller are pcie-pcie bdridge on lshw on linux i sow exactly this but i was hoping was not like this.
If i will have time i will go in my mancave where is my x5000 (i dont turn on it from 1 month)
and will copy and past the log of it just for have better vision of everything.

Seems like the expansion busses and PCI-E routing on these boards is less than ideal.
This is one area the X1000 seems to have a leg up on.
The design of the X5000 could almost be modified for a T10XX.

[ Edited by Jim 13.09.2017 - 09:09 ]

Addendum:

> I doubt Varisys simply forgot to use more than two PCIe controllers, but believe
> there is a good reason for using only two of them. It might be connected to the
> fact that the board has been designed for three different SoCs (P3041, P5020,
> P5040) which are not 100% pin-compatible, so the actual board design
> represents the lowest common denominator between the three SoCs.

I just remembered that 6½ years ago, Jim and I discussed the SerDes assignment options for the P5020's PCIe controllers:

http://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7183&start=154
http://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7183&start=177

As can be seen, the most sane PCIe config for the P5020 used in a desktop computer would have been x4 x4 x1 x1. Now as the P5040 lacks the fourth PCIe controller, this option can't be used on the board, so Varisys had to use the next best option instead, which is x4 x4 (with bridging the 2nd x4 to x8). And even if there was an x4 x4 x1 config for the P5020 (which there isn't), this would have resulted in only 1 lane more (or 3 lanes less without the bridge for the 2nd x4).
I think this should explain why the Cyrus board only uses two PCIe controllers.

but the most intelligent think will be for me if they use the P5021 and not the P5020 for have less problem?
or dont made the 5040 version and only 5020 and P3041 because are Pin compatible. P3041 plus is pin compatible with 4040 and 4080


Quote:

> for them was best made two different board one for 5020 and one for 5040
> put less slots and dont use pcie-pcie bridges and use the 3 pcie controller

If they had made two different boards for X5000/20 and X5000/40, they could have used all four PCIe controllers of the P5020 in x4 x4 x1 x1 config. For the P5040, the only SerDes config that includes SATA and all three PCIe controllers is x4 x1 x1, which is even less lanes than the x4 x4 config used now.
This means having two different boards would have benefited the X5000/20, but not the X5000/40.

29 SerDes assignment configs for P5020
14 SerDes assignment configs for P5040

As you can see, the only matching configs between the SoCs are 0x11, 0x15, 0x2a, 0x34, 0x35 and 0x36. Cyrus uses 0x11.

andreas
but 4x 1x 1x can be good if will gave the best and lest issue compared to put bridge over bridge.
if an user was need a pci for example there are many adaptor on amazon and this will made the mobo probably prizeless for the less components on it.

right now on my x5000 im using only 4x 1x 1x and im ok.

[ Edited by tlosmx 13.09.2017 - 15:28 ]

Well, since the 5040 is essentially pointless (from an "Amiga" perspective), it would have been better to only do *one* board that fully make use of the *5020 specs*. Now they have obviously made compromises to be able to use the same board with a CPU that no Amigan wants or needs.

Jim wanted one.
I did too but opted to get the X5000/20 as my Sam460ex was acting up.

Quote:

*5010 have same specs but can be more amigan

Quote:

There are several "Amigans" who want an X5000 5020 or 5040, who either want it to also run Linux PPC, or still believe that Hyperion has a viable plan for making some kind of "hacky" (wacky) way of eventually getting AmigaOS4.x to utilize more than a single core, without breaking all backward compatibility.

Since I no longer have any faith that Hyperion can accomplish any serious improvements to AmigaOS4, I will ignore them completely, until they have something to show running on my X1000 (like the free upgrade to the imaginary AmigaOS4.2. Doesn't this smell familiarly fishy, like when Hyperion delayed the release of AmigaOS4, just to steal it from Amiga Inc. control via the shady legal agreement/contract, they had gotten Bill Mc fricken Stupid Ewen to sign? Oh wait, I guess it this a different and completely incompetent programming and impossible claims for the OS kind of thing that is preventing Hyperion from completing AmigaOS4.2!)

Quote:

Hardly as an Amigan. Hardly as a Linux user as well (ARM and x86/x64 offers plenty of better options, whatever you need). He is a PPC fetishist, and it still remains to be seen if he will actually put his money where his mouth is in this matter.

Personally, I doubt it.

It's a lot of money.

Quote:

The problem is the "or" in your sentence above, since this option of using the 5040 with the same board design seems to have cripled the board for all 5020 users (and 5020 is less of a *waste* for Amigans than the 5040, hence this is what most Amigans will choose). No doubt the 5040 will be more expensive, it will have 3 unused cores instead of 1, it may be clocked faster but still without being fast at all, not measured against modern hardware, not even measured against 2005 level Mac PPC hardware. Obviously not even in Linux using all 4 cores, where an ancient Quad Powermac easily beats it at the fraction of the price tag.

Quote:

Yes, the problems the 5040 (and even 5020) are having make it less attractive to rational people, but if the 5040 runs AmigaOS4.1FE faster than my X1000, or even just marginally faster than the 5020, there will be a small number of AmigaOS4 fanatics that will pay the price to have the best experience running their beloved AmigaOS4.

None of the Amiga and Amiga inspired options are rational choices today for anything other than nostalgic fun, so it is all just a matter of levels of lunacy in trying to use any of our systems for modern tasks. I see it as similar to many other hobbies, including collecting and/or restoring and reselling antique cars. The money spent is often several times more expensive than the price such antique cars can be sold for, after they have been restored, if the car is old and needs major repairs and/or is missing expensive replacement parts. I think most antique car owners buy them to enjoy for a short while, then sell them at a loss to the next collector, who gets some enjoyment from driving, or just looking at them in their garage. On rare occasions, some of the antique cars will increase in value, depending on the rarity of the model, and the general state of the world economy. Buying the already restored antique cars at auctions can sometimes yield lucky results, and lead to a potential profit, but those opportunities in any hobby I think are fairly rare.

We did discuss this quite a while ago, and now that you go back over it, I guess this is about the optimal configuration.

As these are Gen2 PCI-E lanes, they have twice the bandwidth, so it's really not that bad.

> I actually preferred the X1000's expansion slot setup as the P50xx doesn't offer
> as many PCI-E lanes

Indeed, 23 of the 24 SerDes lanes of the PA6T on the Nemo/X1000 are assigned to PCIe, while only max. 12 of 18 lanes are assignable to PCIe on the P5020 and even only max. 8 of 20 on the P5040. Freescale really didn't cover themselves in glory there.

> Seems like the expansion busses and PCI-E routing on these boards is less than ideal.

That's the price to be paid when having to settle for the lowest common denominator for a board used with two SoCs (three originally) that are not 100% pin-compatible. Given that task and the number and type of expansion slots A-Eon probably requested, Varisys found the ideal solution in selecting x4 x4 config and using a bridge on the 2nd x4 to gain 4 more PCIe lanes for a total of 12.
Varisys can only work with what they get, and they can't overcome Freescale's bad decisions (or A-Eon's, for that matter).

> This is one area the X1000 seems to have a leg up on.

Absolutely, as the PA6T seems to allow an arbitrary SerDes lane assignment, whereas the QorIQ series is really limited in this regard by only allowing to select from a number of fixed assignments (none of which defined with desktop use in mind, of course).

>Indeed, 23 of the 24 SerDes lanes of the PA6T on the Nemo/X1000 are assigned to PCIe, while only max. 12 of 18 lanes are assignable to PCIe on the P5020 and even only max. 8 of 20 on the P5040. Freescale really didn't cover themselves in glory there.

It's probably related to the intended use of the CPUs. The PA6T was intended to be more of a general purpose processor, whereas the the Qorlq line is aimmed at communications devices.

> the most intelligent think will be for me if they use the P5021 and not the P5020
> for have less problem?

The Cyrus Plus board with x4 x4 PCIe config as it is now is already configured optimally for the P5040 (and P5021). Using the P5021 instead of the P5020 would have brought no benefit except of a 2.2 GHz X5000/21 instead of the 2.0 GHz X5000/20. PCIe config would have been the same.

> or dont made the 5040 version and only 5020 and P3041 because are Pin compatible.

Indeed, the P3041 and the P5010/P5020 are both 100% pin-compatible and 100% SerDes config compatible. A board made for them (or just for P5010/P5020) would have meant no compromise in board design and SerDes lane assignment, allowing for x4 x4 x1 x1 PCIe config.

> P3041 plus is pin compatible with 4040 and 4080

P3041/P5010/P5020 are not more compatible with P4040/P4080 than with P5021/P5040 (which doesn't mean the last two groups are more compatible with one another, just in case someone might hit on this idea).

Quote:

Because of the lousy situation the ppc hardware market is in, I advocate the x64 shift since years. ppc is nice, ppc processors may be okay, but boards.... Not to question the comptence of the varisys guys, but I guess ASUS or Dell are just more professional on designing hardware - they are just more experienced. And if one board performes poor, there are plenty that don't.

To make it short: Avoiding ppc - avoidig problems.

> Not to question the comptence of the varisys guys, but I guess ASUS or Dell are just
> more professional on designing hardware - they are just more experienced.

As said, Varisys are certainly not to blame for the design compromises made for the Cyrus/X5000. If anyone is to blame, then it's Freescale/NXP for the limited and incompatible SerDes configs provided in their SoCs, and maybe also A-Eon for commissioning a common board for two sub-100% compatible SoCs and requesting the given number and type of expansion slots at the same time.
I doubt that, given these premises, ASUS or Dell would have provided a better solution to this specific task.

> if one board performes poor [...]

AFAIK, the reason for the poor memory performance of Cyrus/X5000 (clearly contradicting the specs of the memory controller) has not been determined yet. We just know it's not the OS as it's equally poor on Linux, OS4 and MorphOS. This leaves the SoC (memory controller), the board design or the U-Boot firmware as contemplable culprits.

>AFAIK, the reason for the poor memory performance of Cyrus/X5000 (clearly contradicting the specs of the memory controller) has not been determined yet. We just know it's not the OS as it's equally poor on Linux, OS4 and MorphOS. This leaves the SoC (memory controller), the board design or the U-Boot firmware as contemplable culprits.

Hopefully its a configuration or firmware issue that can be rectified in the future.
Obviously it can't be the memory, which is the same sort of DDR3 used in other machines.

If this is something that can be addressed, then its a little early to start throwing up red flags about it.
And we knew about the PCI-E limitations quite awhile ago.