> the soc if one on the topo have to be one only ...
> if you see the image you will see two with same id

You mean the "PCI 1957:0451" ID? If yes, are you sure this is the P5040 SoC?

> L3 cache [...] is used only for corenet and not as sdram
> for be sdram have to be set up in source config of uboot ... but no one setup it. and build.

Then this should be changed in U-Boot. Who is the developer/maintainer of U-Boot for Cyrus/X5000?

> 2 gbs max for 5020
> G5 Quad is 7/8 Gb/s

Yes, I already compared my PowerMac G5 to the X5000 (both with MorphOS) last year and basically came to the same conclusion:

AmigaMARK Memory, stream:
http://morph.zone/modules/newbb_plus/viewtopic.php?forum=11&topic_id=11137&start=593

RAGEMEM:
http://morph.zone/modules/newbb_plus/viewtopic.php?forum=11&topic_id=11137&start=624

> the topology of the cyrrus is totally strange compared all topology in the
> world Informaic Tecnology. qemu dont manage it because strange.

Okay, so the Cyrus board topology is strange, not wrong :-)