>> There's only one SoC on the Cyrus/X5000.

> ... bad because it made the topo more strange than before

Why? I don't see where the lstopo output shows more than one SoC.

> im try to reproduce the board scheme on qemu and it refuse to do something like that.

So you say that the Cyrus board topology is wrong because QEMU can't recreate it? Wouldn't it rather mean that there's something wrong with QEMU if it can't recreate the topology of an existing board?

>>> The L3 cache is a fake cache it is used only for net packet and not for data...

>> I didn't know that the CoreNet L3 cache can't be used also like a normal L3 cache.

> yes it can be used as fast sdram too.

Just like it's supposed to be, right? Everything fine then.

>> this has nothing to do with the board design, don't you think?

> i was referring to the topo scheme.

What's wrong with the L3 cache in the lstopo output?

> my fear is the e5500 true speed is ddr 200 at true 400MTs data rate.

The memory controller is not part of the e5500 core. It's part of the SoC's 'uncore'. Also, 400 MHz and 800 MT/s is minimum spec for DDR3.

https://en.wikipedia.org/wiki/DDR3_SDRAM#JEDEC_standard_modules