Quote:Andreas_Wolf wrote:
>>>
X5000 Topographic>> Thanks. And what's wrong with this topology?
> first the two socs (?) i hope are the sosc not sure have the same id and float around
> someware
There's only one SoC on the Cyrus/X5000.
> the second controller have all the bridge put on it ...
> with bridge over a bridge over a bridge over a bridge...
Actually, it's one PCIe-PCIe bridge with another PCIe-PCI bridge (for the PCI slots) attached to it.
http://morph.zone/modules/newbb_plus/viewtopic.php?forum=11&topic_id=11137&start=712> the third controller pcie controller they forget to use.
I doubt Varisys simply forgot to use more than two PCIe controllers, but believe there is a good reason for using only two of them. It might be connected to the fact that the board has been designed for three different SoCs (P3041, P5020, P5040) which are not 100% pin-compatible, so the actual board design represents the lowest common denominator between the three SoCs.
http://morph.zone/modules/newbb_plus/viewtopic.php?forum=3&topic_id=7001&start=893Considering the fact that the P3041 version was abandoned anyway, they might as well have selected the P5021 instead of the P5020, as the P5021 and the P5040 are 100% pin-compatible.
> The L3 cache is a fake cache it is used only for net packet and not for data...
Interesting. I didn't know that the CoreNet L3 cache can't be used also like a normal L3 cache. But even then this has nothing to do with the board design, don't you think?
> overall deskop performances are choppy, slow expecially after some times.
> i think becasue havy ram granulation.
Do you think this is a board design issue?
> steam report only max 2gb/s for 5020 and 4 gb/s for 5040
Do you think this is a board design issue?
oh mama to much question.
>There's only one SoC on the Cyrus/X5000.
... bad because it made the topo more strange than before,
>one PCIe-PCIe bridge with another PCIe-PCI bridge
ok that can be normal
... but on the topo you see more bridges in the schemas are the squares.
one is the extra bridge of the cmi board (and is normal) many others none.
im try to reproduce the board scheme on qemu and it refuse to do something like that.
it continue make a "normal topo"
shot>Interesting. I didn't know that the CoreNet L3 cache can't be used also like a normal L3 cache. But even then this has nothing to do with the board design, don't you think?
yes it can be used as fast sdram too. but i was referring to the topo scheme.
>Do you think this is a board design issue?
can be it or bad kernel integrations, low ram speed bottle neck.
ram speed so slow... i hope is only bad uboot integration... bur my fear is the e5500 true speed is ddr 200 at true 400MTs data rate.
