> Odd, only one PCI-E X16 and X8 slot? If it has three, and they are split between
> the processors, which one controls the third X16 slot?

The Talos II block diagram published yesterday reveals which slots/controllers are connected to which CPU (used PCIe lane quantity in brackets):

CPU0 (36 lanes used): PCIe (x16+x8), SAS/SATA (x8), Ethernet (x2), USB (x1), BMC (x1)
CPU1 (44 lanes used): PCIe (x16+x16+x8), OCuLink μPCIe (x4)

While the used Sforza module provides 48 PCIe lanes per chip, which in terms of figures would have allowed for CPU1's x8 slot to be connected to CPU0 instead, it can only connect to up to 6 PCIe endpoints. The connections to SAS/SATA, Ethernet, USB and BMC necessary for CPU0 add up to 4 endpoints, leaving endpoints for no more than 2 PCIe slots.
And as can be seen, OCuLink μPCIe won't be available in single-CPU configuration.

[ Edited by Andreas_Wolf 09.03.2018 - 23:55 ]